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AS7331

Functional Description

Datasheet

• PUBLIC

DS001047

• v4-00 • 2023-Mar-24

│ 40

Where:

MRES = Digital output value of the conversion (content of output registers MRES1 to MRES3).

Ee =

Input light irradiance regarding the photodiode’s area within the conversion time interval.

FSREe = Full Scale Range of detectable input light irradiance Ee.

Re = Irradiance responsivity (see Figure 48).

NCLK = Number of clock cycles within the conversion time interval TCONV (see Figure 48).

21+DIV[dec] =

Value of the divider factor respectively prescaler (CREG2:DIV = 7…0), see Figure 49.

The A/D converters of the AS7331 operate with a resolution of 24 bits, but their results are only

provided as 16-bit wide values. The divider allows you to read out the otherwise unavailable upper 8

bits, depending on the value of CREG2:DIV if CREG2:EN_DIV is set to

“1”.

Therefore, the divider acts as a feature to digitally downscale the converter gain, but with a larger full-

scale range (FSR). The effective dynamic range of the device is increased without changing the

conversion time.

Figure 34:

Relation of the Measurement Result to the Conversion Time Without Divider Respectively

Prescaler

Figure 34 shows the width of the register for the conversion time (OUTCONV), which represents the

internal resolution of the A/D conversion. Furthermore,

the measurement result (MRES[1…3]) is

shown, which is 16-bit wide. For all conversion times from 210 to 216, there is no need to use the

divider, because OUTCONV is limited to the conversion time length.

For conversion times bigger than 216, the conversion result is longer than 16 bits. Without the function

of the divider, the result always contain the 16 least significant bits. The divider makes it possible to

access the most significant bits by shifting the 16-bit resolution of the measurement result over the

possible range of the resolution given by the conversion time register (OUTCONV).

Figure 35 shows an example, where CREG2:DIV = 2 dec, and therefore the divider factor is 23. Thus,

MRES corresponds to the bits 18 to 3 of register OUTCONV, making the least significant bits and the

full-scale range eight times higher than if the divider is not used.

12 11 10 9 8 7 6 5 4 3 2

19 18 17 16 15 14 13

23 22 21

12 11 10 9 8 7 6 5 4 3 2

15 14 13

OUTCONV

MRES

CREG2:EN_DIV = ‚0'

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