AS6221T

Register description

Datasheet

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Addr: 0x1

Configuration

Bit

Bit name

Default

Access

Bit description

13

Reserved

0

RO

Reserved

14

Reserved

1

RO

Reserved

15

SS

0

RW

Single Shot

The configuration register is a 16-bit register which defines the operation modes of the device.

Any read/write operation processes the MSB byte first.

In Table 10, the configuration register is shown. The bits 0-4 and 13-14 are not to be used and

are set to read only. The explanation of the other bits are detailed in the following sections.

6.2.2

Alert bit

The alert bit can be used to easily compare the current temperature reading to the thresholds

that can be set in the TLOW and THIGH registers.

If the polarity bit is set to 0, the AL bit is read as 1 until the converted temperature value

exceeds the defined value in the high temperature threshold register THIGH for the number of

defined consecutive faults (bits CF). Such an event causes the AL bit to toggle to 0 and the

value is kept until the converted temperature value falls below the defined value in the low

temperature threshold register TLOW for the number of defined consecutive faults. If this

condition is met, the AL bit is reset to 1.

The polarity bit (POL) defines the active state of the alert bit as depicted in the following figure.

The alert bit has the same setting as the alert output as long as the device is configured for the

comparator mode.

Figure 5: State diagram of the alert bit