AS6221T

Register description

Datasheet

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6.3.15

Timing diagrams

The following timing diagrams depict the different bus operation modes and data transmission:

Figure 10: Timing diagram for word write

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

SDA

1

0

0

R/W

0

0

0

0

0

0

IX1

IX0

Start

by master

Values are defined by

ADD0 pin setting

Frame 1: Slave Address Byte

Frame 2: Index Register Byte

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

SDA

Frame 3: MSB Data Byte

Frame 4: LSB Data Byte

D7

D6

D5

D4

D3

D2

D1

D0

D6

D5

D4

D3

D2

D1

D7

D0

(Continued)

(Continued)

Acknowledge

by slave

Acknowledge

by slave

Acknowledge

by slave

Acknowledge

by slave

Stop

by master

A3

A2

A1

A0

Values are defined

by ALERT/ADD1 pin

setting