AS6221T

Register description

Datasheet

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6.3.6

Slave receiver mode

Any transmission is invoked by the master device by transmitting the slave address with a low

R/W bit. Subsequently, the slave device acknowledges the reception of the valid address by

pulling the ninth bit to a low level. Following to acknowledge, the master transmits the content

of the index register. This transfer is again acknowledged by the slave device. The next data

byte(s) are written to the actual data register which is selected by the index register while each

transfer is acknowledged upon a completed transfer by the slave device. A data transfer can

be finished if the master transmits a START or a STOP condition on the bus.

6.3.7

Slave transmitter

The master transmits the slave address with a high R/W bit. In turn, the slave acknowledges a

valid slave address. Subsequently, the slave transmits the MSB byte of the actual selected

data register by the index register. After the MSB byte transmission, acknowledge is sent by

the master. Afterwards, the LSB byte is transmitted by the slave which is also acknowledged

by the master after the completed transmission. The data transfer can be terminated by the

master by transmitting a Not-Acknowledge after the transmitted slave data or by invoking a

START or a STOP condition on the bus.

6.3.8

Alert function

If the device is configured for an interrupt mode operation (IM=1), the ALERT output can be

used as an alert signal.

If the polarity bit is set to ‘0’ (POL=’0’), the alert condition bit is set to ‘0’ in case the

temperature has exceeded the configured value in register THIGH. Accordingly, the alert

condition bit is set to ‘1’ if the temperature has fallen below the configured value in register

TLOW.

If the polarity bit is set to ‘1’ (POL=’1’), the alert condition bit is inverted. The following table

summarizes the status of the alert condition bit with different alert conditions and polarity

configurations.

Table 22: Alert condition bit

Polarity bit

Alert condition

Alert condition bit (AC-Bit)

0

T ≥ THIGH

0

0

T ≤ TLOW

1

1

T ≥ THIGH

1