AS6221T

Register description

Datasheet

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After completing the data transfer, the master generates a STOP condition by pulling the data

line (SDA) from low level to high level while the clock signal (SCL) is kept at high level.

6.3.2

Data interface

A bus connection is created by connecting the open drain input/output lines SDA and SCL to

the two wire bus. The inputs of SDA and SCL feature Schmitt-trigger inputs as well as low

pass filters in order to suppress noise on the bus line. This improves the robustness against

spikes on the two wire interface.

Both fast transmission mode (1 kHz to 400 kHz) and high-speed transmission mode (1 kHz to

3.4 MHz) are employed to cover different bus speed settings.

Any data transfer transmits the MSB first and the LSB as last bit.

6.3.3

Bus address

A slave address consists of seven bits, followed by a data direction bit (read/write operation).

The slave address can be selected from 8 different address settings by connecting the pin

ADD0 and ADD1 to an appropriate signal as summarized in Table 21.

The ADD0 and the ADD1 pin must not be left unconnected.

The address selection with ADD1 is depending on the usage of the ALERT function (described

in chapter 6.3.8). In case the ALERT functionality is used, it must be connected via a pull up

resistor to VDD. In case the ALERT functionality is not used, the pin must be connected to

either SCL or VSS (refer to Table 21 for details).

Table 21: I²C address select configuration

ALERT / ADD1

connection

ADD0 connection

Alert

functionality

enabled

Device address

(bin)

Device address

(hex)

SCL

VSS

No

101 0100

0x54

SCL

VDD

No

101 0101

0x55

SCL

SDA

No

101 0110

0x56

SCL

SCL

No

101 0111

0x57

VSS

VSS

No

101 1000

0x58

VSS

VDD

No

101 1001

0x59

VSS

SDA

No

101 1010

0x5A

VSS

SCL

No

101 1011

0x5B