MPC8323ECVRADDC datasheet(33/80 Pages) FREESCALE

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Figure 23 provides the AC test load for the I2C.

Figure 23. I2C AC Test Load

Figure 24 shows the AC timing diagram for the I2C bus.

Figure 24. I2C Bus AC Timing Diagram

Rise time of both SDA and SCL signals

tI2CR

20 + 0.1 Cb

300

Fall time of both SDA and SCL signals

tI2CF

20 + 0.1 Cb

300

Setup time for STOP condition

tI2PVKH

0.6

—

μs

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs

Noise margin at the LOW level for each connected device (including

hysteresis)

VNL

0.1

× OVDD

—V

Noise margin at the HIGH level for each connected device (including

hysteresis)

VNH

0.2

× OVDD

—V

Notes:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing (I2)

with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high

(H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. MPC8323E provides a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) to bridge

the undefined region of the falling edge of SCL.

3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.

4. CB = capacitance of one bus line in pF.

Table 34. I2C AC Electrical Specifications (continued)

All values refer to VIH (min) and VIL (max) levels (see Table 33).

Parameter

Symbol1

Min

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

SDA

SCL

tI2CF

tI2SXKL

tI2CL

tI2CH

tI2DXKL

tI2DVKH

tI2SXKL

tI2SVKH

tI2KHKL

tI2PVKH

tI2CR

tI2CF

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