MPC8323ECVRADDC datasheet(44/80 Pages) FREESCALE

44 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

HDLC, BISYNC, Transparent, and Synchronous UART

19.1

HDLC, BISYNC, Transparent, and Synchronous UART DC

Electrical Characteristics

Table 50 provides the DC electrical characteristics for the MPC8323E HDLC, BISYNC, transparent, and

synchronous UART protocols.

19.2

HDLC, BISYNC, Transparent, and Synchronous UART AC Timing

Specifications

Table 51 provides the input and output AC timing specifications for HDLC, BISYNC, and transparent

UART protocols.

Table 50. HDLC, BISYNC, Transparent, and Synchronous UART DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

VOH

IOH = –2.0 mA

2.4

—

Output low voltage

VOL

IOL = 3.2 mA

—

0.5

Input high voltage

VIH

—2.0

OVDD +0.3

Input low voltage

VIL

—

–0.3

0.8

Input current

IIN

0 V

≤ VIN ≤ OVDD

—

±5

μA

Table 51. HDLC, BISYNC, and Transparent UART AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

Outputs—Internal clock delay

tHIKHOV

05.5

Outputs—External clock delay

tHEKHOV

110

Outputs—Internal clock high impedance

tHIKHOX

05.5

Outputs—External clock high impedance

tHEKHOX

Inputs—Internal clock input setup time

tHIIVKH

6ns

Inputs—External clock input setup time

tHEIVKH

4ns

Inputs—Internal clock input hold time

tHIIXKH

0ns

Inputs—External clock input hold time

tHEIXKH

1ns

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings

are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs

internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).

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