MPC8323ECVRADDC datasheet(12/80 Pages) FREESCALE

12 / 80 page

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

RESET Initialization

This section describes the AC electrical specifications for the reset initialization timing requirements of

the MPC8323E. Table 9 provides the reset initialization AC timing specifications for the reset

component(s).

Table 10 provides the PLL lock times.

Table 9. RESET Initialization Timing Specifications

Parameter/Condition

Min

Max

Unit

Notes

Required assertion time of HRESET or SRESET (input) to activate reset

flow

—

tPCI_SYNC_IN

Required assertion time of PORESET with stable clock applied to CLKIN

when the MPC8323E is in PCI host mode

—

tCLKIN

Required assertion time of PORESET with stable clock applied to

PCI_SYNC_IN when the MPC8323E is in PCI agent mode

—

tPCI_SYNC_IN

HRESET/SRESET assertion (output)

512

—

tPCI_SYNC_IN

HRESET negation to SRESET negation (output)

—

tPCI_SYNC_IN

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to

negation of PORESET when the MPC8323E is in PCI host mode

4—

tCLKIN

Input setup time for POR configuration signals

(CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to

negation of PORESET when the MPC8323E is in PCI agent mode

4—

tPCI_SYNC_IN

Input hold time for POR config signals with respect to negation of

HRESET

0—

Time for the MPC8323E to turn off POR configuration signals with respect

to the assertion of HRESET

—4

Time for the MPC8323E to turn on POR configuration signals with respect

to the negation of HRESET

1—

tPCI_SYNC_IN

1, 3

Notes:

1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the MPC8323E is In PCI host mode the

primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for more details.

2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the MPC8323E is in PCI host mode. See

the

MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Reference Manual for more details.

3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.

Table 10. PLL Lock Times

Parameter/Condition

Min

Max

Unit

Notes

PLL lock times

—

100

μs

MPC8323ECVRADDC 数据表(PDF) 12 Page - Freescale Semiconductor, Inc

MPC8323ECVRADDC 数据表(HTML) 12 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表下载

链接网址

MPC8323ECVRADDC 数据表(PDF) 12 Page - Freescale Semiconductor, Inc

MPC8323ECVRADDC 数据表(HTML) 12 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

数据表 下载

链接网址

数据表下载