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MPC8323ECVRADDC 数据表(PDF) 39 Page - Freescale Semiconductor, Inc |
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MPC8323ECVRADDC 数据表(HTML) 39 Page - Freescale Semiconductor, Inc |
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39 / 80 page ![]() MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0 Freescale Semiconductor 39 SPI 16 SPI This section describes the DC and AC electrical specifications for the SPI of the MPC8323E. 16.1 SPI DC Electrical Characteristics Table 44 provides the DC electrical characteristics for the MPC8323E SPI. 16.2 SPI AC Timing Specifications Table 45 and provide the SPI input and output AC timing specifications. Figure 30 provides the AC test load for the SPI. Figure 30. SPI AC Test Load Table 44. SPI DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Output high voltage VOH IOH = –6.0 mA 2.4 — V Output low voltage VOL IOL = 6.0 mA — 0.5 V Output low voltage VOL IOL = 3.2 mA — 0.4 V Input high voltage VIH —2.0 OVDD +0.3 V Input low voltage VIL — –0.3 0.8 V Input current IIN 0 V ≤ VIN ≤ OVDD — ±5 μA Table 45. SPI AC Timing Specifications1 Characteristic Symbol2 Min Max Unit SPI outputs—Master mode (internal clock) delay tNIKHOV 0.5 6 ns SPI outputs—Slave mode (external clock) delay tNEKHOV 28 ns SPI inputs—Master mode (internal clock) input setup time tNIIVKH 6— ns SPI inputs—Master mode (internal clock) input hold time tNIIXKH 0— ns SPI inputs—Slave mode (external clock) input setup time tNEIVKH 4— ns SPI inputs—Slave mode (external clock) input hold time tNEIXKH 2— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V). Output Z0 = 50 Ω OVDD/2 RL = 50 Ω |
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