MPC8323ECVRADDC datasheet(67/80 Pages) FREESCALE

部件名	MPC8323ECVRADDC

功能描述	PowerQUICC??II Pro Integrated Communications Processor Family Hardware Specifications

PDF	80 Pages

Scroll/Zoom	100%

制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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MPC8323E PowerQUICC™ II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Clocking

22.5

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 60 shows the encodings for RCWL[COREPLL]. COREPLL values not listed

in Table 60 should be considered reserved.

NOTE

Core VCO frequency = core frequency × VCO divider

VCO divider (RCWL[COREPLL[0:1]]) must be set properly so that the

core VCO frequency is in the range of 500–800 MHz.

Table 60. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider

0-1

2-5

0000

PLL bypassed

(PLL off,

csb_clk clocks

core directly)

PLL bypassed

(PLL off,

csb_clk clocks

core directly)

0001

01:1

÷2

0001

01:1

÷4

0001

01:1

÷8

0001

01:1

÷8

0001

11.5:1

÷2

0001

11.5:1

÷4

0001

11.5:1

÷8

0001

11.5:1

÷8

0010

02:1

÷2

0010

02:1

÷4

0010

02:1

÷8

0010

02:1

÷8

0010

12.5:1

÷2

0010

12.5:1

÷4

0010

12.5:1

÷8

0010

12.5:1

÷8

0011

03:1

÷2

0011

03:1

÷4

0011

03:1

÷8

0011

03:1

÷8

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