ADIS16204

Rev. 0 | Page 5 of 24

TIMING SPECIFICATIONS

Table 2.

Parameter

Description

Min1

Typ

Max1

Unit

Fast mode2

0.01

2.5

MHz

Normal mode2

0.01

1.0

MHz

Chip select period, fast mode2

40

μs

Chip select period, normal mode2

100

μs

Chip select high

Chip select to clock edge

48.8

ns

Data output valid after SCLK edge

100

ns

Data input setup time before SCLK rising edge

24.4

ns

Data input hold time after SCLK rising edge

48.8

ns

Data output fall time

5

12.5

ns

Data output rise time

5

12.5

ns

CS high after SCLK edge

5

ns

CS

SCLK

Figure 2. SPI Chip Select Timing

CS

SCLK

DOUT

DIN

12

3

4

5

6

15

16

W/R

A5

A4

A3

A2

D2

MSB

DB14

D1

LSB

DB13

DB12

DB10

DB11

DB2

LSB

DB1

Figure 3. SPI Timing

(Utilizing SPI Settings Typically Identified as Phase = 1, Polarity = 1)