ADIS16204

Rev. 0 | Page 12 of 24

BASIC OPERATION

The ADIS16204 is designed for simple integration into industrial

system designs, requiring only a power supply and a 4-wire,

industry-standard SPI. The SPI provides access to the ADIS16204’s

register structure, which controls access to all sensor output data

and controls for the device’s programmable features. Each register

is 16 bits in length and has its own unique bit map. The 16 bits

in each register consist of an upper byte (Bit 8 to Bit 15) and a

lower byte (Bit 0 to Bit 7), each of which has its own 6-bit address.

SERIAL PERIPHERAL INTERFACE

The ADIS16204 SPI port includes four signals: chip select

(CS), serial clock (SCLK), data input (DIN), and data output

(DOUT). The CS line enables the ADIS16204 SPI port and

frames each SPI event. When this signal is high, the DOUT

lines are in a high impedance state and the signals on DIN

and SCLK have no impact on operation. A complete data frame

contains 16 clock cycles. Because the SPI port operates in full

duplex mode, it supports simultaneous, 16-bit receive (DIN)

and transmit (DOUT) functions during the same data frame.

See Table 2, Figure 2, and Figure 3 for detailed timing and

operation of the SPI port.

Writing to Registers

Figure 21 displays a typical data frame for writing a command

to a control register. In this case, the first bit of the DIN sequence

is a 1, followed by a 0, the 6-bit address, and the 8-bit data com-

mand. Because each write command covers a single byte of

data, two data frames are required when writing to the entire

16-bit space of a register. The DIN bits clock into the ADIS16204

on the rising edge of SCLK.

Reading from Registers

Reading the contents of a register requires a modification to

the sequence in the DIN sequence Figure 21. As shown in

Figure 22, the first two bits in the DIN sequence are 0, followed

by six address bits. Each register has two addresses (upper, lower),

but either one can be used to access its entire 16 bits of data. The

final 8 bits of the DIN sequence are irrelevant and can be counted

as don’t cares during a read command. During the next data

frame, the DOUT sequence contains the register’s 16-bit data.

The ADIS16204 clocks out the first DOUT bit on the falling edge

of the CS line and clocks out the rest of the DOUT bits on the

falling edges of the SCLK signal. Although a single read command

requires two separate data frames, the full duplex mode mini-

mizes this overhead, requiring only one extra data frame when

continuously sampling.

CS

SCLK

DIN

W/R

A5

A4

A3

A2

A1

A0

DC7

DC6

DC5

DC4

DC3

DC2

DC1

DC0

DATA FRAME

WRITE = 1

READ = 0

REGISTER ADDRESS

DATA FOR WRITE COMMANDS

DON’T CARE FOR READ COMMANDS

Figure 21. DIN Bit Sequence

ADDRESS

DON’T CARE

NEXT COMMAND

BASED ON PREVIOUS COMMAND

DATA FRAME

16-BIT REGISTER CONTENTS

CS

SCLK

DIN

DOUT

W/R BIT

ZERO

DATA FRAME

Figure 22. SPI Sequence for Read Commands