ADIS16204SLASHPCBZ datasheet(18/24 Pages) AD

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ADIS16204

Rev. 0 | Page 18 of 24

STATUS Conditions

The STATUS register contains the following error-condition

flags: alarm conditions, self-test status, SPI communication

failure, capture buffer full, control register update failure, and

power supply out of range. See Table 27 and Table 28 for the

appropriate register access and bit assignment for each flag.

The bits assigned for checking power supply range automati-

cally reset to zero when the error condition no longer exists.

Clearing the remaining error-flag bits requires a single write

command to the COMMAND register (write a 1 to Bit 4).

See Table 8 and Table 9 for the configuration details of the

COMMAND register. If the error condition still exists after

exercising the COMMAND register to clear the bits, the appro-

priate error flag bit returns to 1 during the next sampling cycle.

All bits in the STATUS register are volatile.

Table 27. STATUS Register Definition

Address

Default

Format

Access

0x3D, 0x3C

0x0000

N/A

R only

Table 28. STATUS Bit Descriptions

Bit

Description

15:13

Not used

Capture buffers full

11:10

Not used

Alarm 2 status

1 = active, 0 = inactive

Alarm 1 status

1 = active, 0 = inactive

7:6

Not used

Self-test diagnostic error flag

1 = error condition, 0 = normal operation

Not used

SPI communications failure

1 = error condition, 0 = normal operation

Flash update failed

1 = error condition, 0 = normal operation

Power supply above 3.625 V

1 = above 3.625 V, 0 = below 2.975 V (normal)

Power supply below 2.975 V

1 = below 2.975 V, 0 = above 2.975 V (normal)

ALARM DETECTION AND EVENT CAPTURE

The ADIS16204 provides alarm detection and event capture

functions, which monitor critical internal and external

operating conditions. Six factory standard alarms monitor

the AIDS16204 for normal operation. Two programmable

alarms provide monitoring for system-critical conditions,

which reduces external processing burden for this function.

Alarm monitoring includes both software (STATUS register)

and hardware options (DIO1 and DIO2 configuration,

ALM_CTRL register). In addition, the programmable alarms

can trigger an event capture function, which provides time

recording, much like a single event capture function on a digital

oscilloscope. Table 29 provides a summary of the functions

available for configuring the alarms.

Alarm Configuration

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Program The Output Data To Monitor.

Essentially, this establishes the trigger source, by configuring

the upper byte of the ALM_CTRL register. See Table 31 for the

proper bit assignments. For example, the following pseudo code

establishes X acceleration as the trigger for Alarm 2 and Y accel-

eration as the trigger for Alarm 1:

•

Write 0x23 to Address 0x29 [ALM_CTRL].

Program The Trigger Levels And Polarity.

This requires two write commands for each alarm, to the

ALM_MAG1 and ALM_MAG2 registers. For example, use

the following pseudo code to establish greater than 7.4 g as

the trigger threshold for both channels:

•

Write 0x81 to Address 0x21 [ALM_MAG1].

•

Write 0xB0 to Address 0x20 [ALM_MAG1].

•

Write 0x83 to Address 0x23 [ALM_MAG2].

•

Write 0x70 to Address 0x22 [ALM_MAG2].

The ALM_MAG1 and ALM_MAG2 values are calculated by:

X = 7.4 g = 432 codes = 00 0001 1011 0000 (Bit 0 to Bit 13)

Y = 7.4 g = 880 codes = 00 0011 0111 0000 (Bit 0 to Bit 13)

Bit 15 in both registers must be set to 1 in order to denote

greater than polarity.

Set Up A Digital I/O Line As An Alarm Indicator.

This step requires configuration of the lower byte in the

ALM_CTRL. If software monitoring, using the STATUS

step is not required. The following pseudo code establishes

Digital I/O Line 2 as a positive signal, alarm indicator:

•

Write 0x07 to Address 0x28 [ALM_CTRL].

See Table 31 for the configuration options available for this

function. As noted earlier, the digital I/O lines are shared, so

use of them as an alarm indicator requires that it not be in use

as a data-ready or general-purpose I/O pin.

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