ADIS16204SLASHPCBZ datasheet(20/24 Pages) AD

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ADIS16204

Rev. 0 | Page 20 of 24

Configure the Capture Back-up Memory.

Setting Bit 11 of the MSC_CTRL register to a 1 enables the

event capture back-up function, effectively making it nonvolatile.

When enabled, this function copies the contents of the capture

buffer (right after it fills) to flash memory and restores it upon

reset or powering the device on. It continues to do so until the

buffer is cleared, using the COMMAND register. To enable this

feature, use the following pseudo code:

•

Write 0x08 to Address 0x35 [MSC_CTRL].

Clear The Capture Memory Locations.

Use the following pseudo code to clear both the normal capture

locations (SRAM) and their respective flash memory locations:

•

Write 0x03 to Address 0x3F [COMMAND].

Set Up A Digital I/O Line As An Alarm Indicator.

Set Each Alarm As A Trigger Source For The Buffer.

These steps require configuration of the lower byte in the

ALM_CTRL register. The following pseudo code establishes

Digital I/O Line 2 as a positive signal, alarm indicator, if

necessary. It also arms both triggers for the event recorder.

•

Write 0x57 to Address 0x28 [ALM_CTRL].

If a digital alarm indicator function were not required, the

pseudo code would be:

•

Write 0x50 to Address 0x28 [ALM_CTRL].

Table 35. CAPT_CFG Register Definition

Address

Scale

Default

Format

Access

0x39, 0x38

N/A

0x327A

N/A

R/W

Table 36. CAPT_CFG Bit Descriptions

Bit

Description

15:12

Data source for Capture Buffer 2

0001= power supply

0010= X-axis acceleration

0011= Y-axis acceleration

0100= auxiliary ADC

0101= temperature sensor

1000= XY RSS acceleration

11:8

Data source for Capture Buffer 1

(See Capture Buffer 2 for binary coding)

7:4

Pretrigger Length:

Power of two setting determines length.

0111b = 7d, which corresponds to 27 = 128 samples. If

this setting is greater than the data length, its value is

truncated and all captured samples are prior to the trigger

3:0

Capture buffer length:

Power of two setting determine length.

1010b = 10d, which corresponds to 210 = 1024 samples.

The lowest setting is a 3, which corresponds to 8

samples

Event Capture Data Access

Two output registers provide the necessary access for the

ADIS16204’s capture buffers: CAPT_BUF_1 and CAPT_BUF_2.

At the completion of a capture event, the contents of theses

registers contain the first sample from each buffer. Figure 25

provides a diagram that displays the role played by the

CAPT_PNTR register in this process. This register provides a

pointer function and automatically increments every time

one of the CAP_BUF_x registers are read. If efficient data

transfer rates are a primary goal, then read all of the contents

of one buffer, before moving to the other buffer. Because the

CAPT_PNTR offers both read and write access, individual

buffer locations can be accessed by writing the sample number

into this register.

CAPT_PNTR

BUFFER 1

BUFFER 2

CAPT_BUF_1

CAPT_BUF_2

USER ACCESIBLE

INTERNAL MEMORY STRUCUTRE

Figure 25. Event Capture Buffer Memory Structure

Table 37. Capture Register Definitions

Address

Format

Access

CAPT_BUF_1

0x1D, 0x1C

CAPT_BUF_2

0x1E, 0x1F

The format and scale

match that of the

output data being

monitored

R only

Table 38. CAPT_BUF_1 and CAPT_BUF_2 Bit Descriptions

Bit

Description

Not used

Error/alarm condition (use to identify transition between

pre-trigger and post-trigger data)

13:0

Data bits. Format matches that of the data source

Table 39. CAPT_PNTR Register Definition

Address

Scale

Default

Format

Access

0x2B, 0x2A

N/A

Binary

R/W

Table 40. CAPT_PNTR Bit Descriptions

Bit

Description

15:11

Not used

10:0

Capture address pointer: A binary number from 1 to

1024, which identifies the address of each individual

capture buffer sample.

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