ADIS16204

Rev. 0 | Page 16 of 24

Table 13. YACCL_SCALE Register Definition

Address

Scale1

Default2

Format

Access

0x17, 0x16

0.0488%

0x0800

Binary

R/W

Table 14. Calibration Register Bit Descriptions

Bit

Description

15:12

Not used

11:0

Data bits

OPERATIONAL CONTROL

Internal Sample Rate

The internal sample rate defines how often data output variables

are updated, independent of the rate at which they are read out

on the SPI port. The SMPL_PRD register controls the ADIS16204

internal sample rate and has two parts: a selectable time base and

a multiplier. The following relationship produces the sample rate:

B

S

+ 1)

where:

N

B

S

is the increment setting.

The default value is the maximum 4096 SPS, and the contents of

this register are nonvolatile.

Table 15. SMPL_PRD Register Definition

Address

Default

Format

Access

0x37, 0x36

0x0001

N/A

R/W

Table 16. SMPL_PRD Bit Descriptions

Bit

Description

15:8

Not used

7

Time base

0 = 122.07 μs, 1 = 3.784 ms

6:0

Multiplier

Here is an example calculation of the sample period for the

ADIS16204:

If SMPL_PRD = 0x0007, B7 − B0 = 00000111

B

B

S

+ 1) = 122.07 μs × (7 + 1) = 976.56 μs

The sample rate setting has a direct impact on the SPI data

rate capability. For sample rates of 1024 SPS and above, the SPI

SCLK can run at a rate up to 2.5 MHz. For sample rates below

1024 SPS, the SPI SCLK can run at a rate up to 1 MHz.

The sample rate setting also affects the power dissipation.

When the sample rate is set below 1024 SPS, the power

dissipation typically reduces by a factor of 68%. The two

different modes of operation offer a system-level trade-off

between performance (sample rate, serial transfer rate) and

power dissipation.

Power Management

In addition to offering two different performance modes for

power optimization, the ADIS16204 offers a programmable

shutdown period. Writing the appropriate sleep time to the

SLP_CNT register shuts the device down for the specified

time. The following example provides an illustration of this

relationship:

B7 … B0 = 00000110

Sleep period = 3 seconds

After completing the sleep period, the ADIS16204 returns to

normal operation.

Table 17. SLP_CNT Register Definition

Address

Scale1

Default

Format

Access

0x3B, 0x3A

0.5 sec

0x0000

Binary

W only

Table 18. SLP_CNT Bit Descriptions

Bit

Description

15:8

Not used

7:0

Data bits

Auxiliary DAC

The auxiliary DAC provides a 12-bit level adjustment function.

The AUX_DAC register controls the operation of this feature.

It offers a rail-to-rail buffered output that has a range of 0 V to

2.5 V. The DAC can drive its output to within 5 mV of the

ground reference when it is not sinking current. As the output

approaches ground, the linearity begins to degrade (100 LSB

beginning point). As the sink current increases, the nonlinear

range increases. The DAC output latch function, contained in

the COMMAND register, provides continuous operation while

writing to each byte of this register. The contents of this register

are volatile, which means that the desired output level must be

set after every reset and power cycle event.

Table 19. AUX_DAC Register Definition

Address

Scale1

Default

Format

Access

0x31, 0x30

0.6105 mV

0x0000

Binary

R/W

the 2.5 V range out of output voltage.

Table 20. AUX_DAC Bit Descriptions

Bit

Description

15:12

Not used

11:0

Data bits