ADIS16204

Rev. 0 | Page 17 of 24

General-Purpose I/O

The ADIS16204 provides two general-purpose pins that

enable digital I/O control using the SPI. The GPIO_CTRL

control register establishes the configuration of these pins

and handles the SPI-to-pin controls. Each pin provides the

flexibility of both input (read) and output (write) operations.

For example, writing a 0x0202 to this register establishes Line 1

as an input and Line 2 as an output that is in a 1 state. Writing

0x0000 to this register establishes both lines as inputs. When

one (or both) of these lines is configured as an input, reading

the assigned bit (Bit 8 and/or Bit 9) provides access to the input

on this input pin.

The digital I/O lines are also available for data-ready and alarm/

error indications. In the event of conflict, the following priority

structure governs the digital I/O configuration:

1.

GPIO_CTRL

2.

MSC_CTRL

3.

ALM_CTRL

Table 21. GPIO_CTRL Register Definition

Address

Default

Format

Access

0x33, 0x32

0x0000

N/A

R/W

Table 22. GPIO_CTRL Bit Descriptions

Bit

Description

15:10

Not used

9

General-purpose I/O Line 2 polarity

1 = high, 0 = low

8

General-purpose I/O Line 1 polarity

1 = high, 0 = low

7:2

Not used

1

General-purpose I/O Line 2, data direction control

1 = output, 0 = input

0

General-purpose I/O Line 1, data direction control

1 = output, 0 = input

STATUS AND DIAGNOSTICS

The ADIS16204 provides a number of status and diagnostic

functions. Table 23 provides a summary of these functions,

along with their appropriate control registers.

Table 23. Status and Diagnostic Functions

Function

Register

Data-ready I/O indicator

MSC_CTRL

Self-test, mechanical check for MEMS sensor

MSC_CTRL

Software check for error conditions

STATUS

Flash memory endurance

ENDURANCE

Data-Ready I/O Indicator

The data-ready function provides an indication of new output

data. The MSC_CTRL register provides the opportunity to

configure either of the general-purpose I/O pins (DIO1 and DIO2)

as a data-ready indicator signal. When configured as a data ready

indicator, the duty cycle is 20% (±10% tolerance).

Self-Test

The MSC_CTRL register also provides a self-test function

that verifies the mechanical integrity of the MEMS sensor. Self-

test exercises the mechanical structure and signal conditioning

circuit: from sensor element to data out. The internal test provides

a simple, two-step process for checking the MEMS sensor: (1)

start the process by writing a 1 to Bit 8 in the MSC_CTRL

register, (2) wait 35 ms, and (3) check the result by reading

Bit 5 of the STATUS register.

The device is configured to perform a self-test at power on.

Writing a 1 to Bit 10 of the MSC_CTRL register disables this

function for future start-up sequences, reducing the start-up

time. For reference, the result of the electrostatic deflection

of each axis is available by reading the XACCL_OUT and/or

YACCL_OUT registers. As an additional indicator of self-test,

the new data bit is not active while in this mode.

Table 24. MSC_CTRL Register Definition

Address

Default

Format

Access

0x35, 0x34

0x0000

N/A

R/W

Table 25. MSC_CTRL Bit Descriptions

Bit

Description

15:12

Not used

11

Store capture to flash after capture buffer fills up

1 = enabled, 0 = disabled

10

Self-test at power-on:

1 = disabled, 0 = enabled

9

Not used

8

Self-test enable (temporary, bit is volatile)

1 = enabled, 0 = disabled

7:3

Not used

2

Data-ready enable

1 = enabled, 0 = disabled

1

Data-ready polarity

1 = active high, 0 = active low

0

Data-ready line select:

1 = DIO2, 0 = DIO1

Flash Memory Endurance

The ENDURANCE register maintains a running count of writes to

the flash memory. This provides a convenient tool for managing

the reliability of the on-chip memory. Once it reaches its maxi-

mum value of 32,767, it wraps around to zero and starts over.

Table 26. ENDURANCE Register Definition

Address

Default

Format

Access

0x01, 0x00

N/A

Binary

R only