ADIS16204SLASHPCBZ datasheet(14/24 Pages) AD

14 / 24 page

ADIS16204

Rev. 0 | Page 14 of 24

PROGRAMMING AND CONTROL

CONTROL REGISTER OVERVIEW

The ADIS16204 offers many programmable features controlled

by writing commands to the appropriate control registers. The

following features are available for configuration:

•

Global commands

•

Calibration

•

Operational control

•

Sample rate

•

Power management

•

DAC output

•

Digital I/O

•

Operational status and diagnostics

•

Self-test

•

Status conditions

•

Alarms

•

Event capture

CONTROL REGISTER STRUCTURE

The ADIS16204 uses a temporary, SRAM-based memory struc-

ture to facilitate the control registers displayed in Table 7. The

start-up configuration is stored in a flash memory structure that

automatically loads into the control registers during the start-up

sequence. Each nonvolatile register has a corresponding flash

memory location for storing the latest configuration contents.

Because flash memory has endurance limitations, the contents

of each nonvolatile register must be stored to flash manually.

Note that the contents of the control register are only nonvola-

tile when they are stored to flash. The flash update command,

made available in the COMMAND register, provides this function.

The ENDURANCE register provides a counter, which allows

for memory reliability management against the flash memory’s

write cycle specification.

Table 7. Control Register Mapping

Name

Type

Volatility1

Address

Bytes

Function

Reference Table

ENDURANCE

Nonvolatile

0x01, 0x00

Flash memory write counter

Table 26

0x02 to 0x0F

Output data registers

Table 6

XACCL_NULL

R/W

Nonvolatile

0x11, 0x10

X-axis offset null calibration register

Table 10

YACCL_NULL

R/W

Nonvolatile

0x13, 0x12

Y-axis offset null calibration register

Table 11

XACCL_SCALE

R/W

Nonvolatile

0x15, 0x14

X-axis scale factor calibration register

Table 12

YACCL_SCALE

R/W

Nonvolatile

0x17, 0x16

Y-axis scale factor calibration register

Table 13

0x18 to to 0x1B

Output data registers

Table 6

CAP_BUF_1

Volatile

0x1D, 0x1C

Capture buffer output register 1

Table 37, Table 38

CAP_BUF_2

Volatile

0x1F, 0x1E

Capture buffer output register 2

Table 37, Table 38

ALM_MAG1

R/W

Nonvolatile

0x21, 0x20

Alarm 1 amplitude threshold

Table 32, Table 34

ALM_MAG2

R/W

Nonvolatile

0x23, 0x22

Alarm 2 amplitude threshold

Table 33, Table 34

0x24 to 0x27

Reserved

ALM_CTRL

R/W

Nonvolatile

0x29, 0x28

Alarm source control register

Table 30, Table 31

CAPT_PNTR

R/W

Volatile

0x2B, 0x2A

Capture register address pointer

Table 39, Table 40

0x2A to 0x2F

Reserved

AUX_DAC

R/W

Volatile

0x31, 0x30

Auxiliary DAC data

Table 19, Table 20

GPIO_CTRL

R/W

Volatile

0x33, 0x32

Auxiliary digital I/O control register

Table 21, Table 22

MSC_CTRL

R/W

Nonvolatile2

0x35, 0x34

Miscellaneous control register

Table 24, Table 25

SMPL_PRD

R/W

Nonvolatile

0x37, 0x36

ADC sample period control register

Table 15, Table 16

CAPT_CFG

R/W

Nonvolatile

0x39, 0x38

Capture configuration register

Table 35, Table 36

SLP_CNT

Volatile

0x3B, 0x3A

Counter used to determine length of

power-down mode

Table 17, Table 18

STATUS

Volatile

0x3D, 0x3C

System status register

Table 27, Table 28

COMMAND

N/A

0x3F, 0x3E

System command register

Table 8, Table 9

1 In order to establish nonvolatile status, the flash memory must be updated after updating the control registers.

2 Bit 8 clears after the internal self-test sequence completes, effectively making this bit volatile.

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