LTM4659EVPBF datasheet(13/26 Pages) AD

13 / 26 page

LTM4659

Rev. 0

For more information www.analog.com

Once the soft-start cycle has been completed and the

output power good flag has been thrown, the SSTT pin

reports the die junction temperature. The LTM4659 regu-

lates the SSTT pin to a voltage proportional to the junction

temperature. While reporting the temperature, the SSTT

voltage is not valid below 1V. The junction temperature

is calculated using Equation 6.

TJ (°C) =

VSSTT

4mV

– 273

(6)

The following procedure is used for a more accurate mea-

surement of the junction temperature.

1. Measure the ambient temperature TA.

2. Measure the SSTT voltage while in PSM with the VOUT

pulled up slightly higher than the regulated VOUT.

3. Calculate the slope of the temperature sensing circuit

using Equation 7.

Slope mV

°C

⎛

⎝

⎜

⎞

⎠

⎟=

VSSTT

TA + 273

(7)

4. Calculate the junction temperature with the new cali-

brated slope.

When the output voltage goes out of regulation and the

power good pin is pulled low, the soft-start pin no longer

reports the temperature.

Power Good

The PGOOD pins are open-drain pins that can be used to

monitorvalidoutputvoltageregulation.Thispinmonitorsa

−3/10%windowaroundtheregulationpoint.Aresistorcan

be pulled up to a particular supply voltage for monitoring.

To prevent unwanted PGOOD glitches during transients

or dynamic VOUT changes, the LTM4659’s PGOOD falling

edgeincludesablankingdelayofapproximately100µs.The

PGOOD is also actively pulled low during fault conditions:

RUN pin is low, VIN is too low, or in thermal shutdown.

Transient Response and Loop Compensation

When determining the compensation components, CFF,

RC, and CC, control loop stability and transient response

are the two main considerations. The LTM4659 has been

designed to operate at high bandwidth for fast transient

response capability. Operating at a high loop bandwidth

reduces the output capacitance required to meet transient

response requirements. Applying a load transient and

monitoring the system’s response or using a network ana-

lyzer to measure the actual loop response are two ways

to verify and optimize LTM4659. For more information,

refer to the Analog Devices technical article: “Understand

Power Supply Loop Stability and Loop Compensation—

Part 1: Basic Concepts and Tools”. Analog Devices

LTpowerCAD is a useful tool for optimizing the compen-

sation components.

When using the load transient response method to sta-

bilize the control loop, apply an output current pulse of

20% to 100% of the full load current having a rise time

of 1µs. This will produce a transient on the output voltage

and COMP pin waveforms.

Switching regulators take multiple cycles to respond

to a step in load current. When a load step occurs,

VOUT is immediately perturbed, generating a feedback

error signal used by the regulator to return VOUT to its

steady-state value.

During this recovery time, monitor VOUT for overshoot

or ringing indicating a stability problem. The initial out-

put voltage step may not be within the bandwidth of the

feedback loop, so the standard second-order overshoot/

DC ratio cannot be used to determine the phase margin.

The gain of the loop increases with the RC, and the band-

width of the loop increases with decreasing CC. If RC is

increased by the same factor that CC is decreased, the

zero frequency will be kept the same, thereby keeping the

phase the same in the most critical frequency range of the

feedback loop. In addition, adding a feedforward capaci-

tor, CFF, improves the high frequency response. Capacitor

CFF provides phase lead by creating a high-frequency zero

with RA to improve the phase margin. The compensation

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