LTM4659

19

Rev. 0

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Table 8. Output Voltage Response vs Component Matrix (See Typical Application) 0A to 5A Load Step Typical Measured Values

CIN CERAMIC

VENDORS

VALUE

(μF)

PART NUMBER

COUT VENDORS

VALUE

(μF)

PART

NUMBER

Taiyo Yuden

10

EMK212BB7106MG-T

Murata

22

GRM188R60J226MEA0D

Murata

22

GRM188R61A226ME15D

Murata

100

GRM21BR60J107ME15K

VOUT

(V)

CIN

(CERAMIC)

(μF)

CIN

(BULK)

COUT

(CERAMIC)

(μF)

CFF

(pF)

VIN

(V)

DROOP

(mV)

P-P

Deviation

(mV)

RECOVERY

TIME

(µs)

LOAD STEP

(A/µs)

LOAD STEP

SLEW RATE

(A/µs)

FREQ.

(kHz)

0.5

10 ×2

150

100 + 22 ×2

Open

3.3

40

78

5

5

5

1000

0.8

10 ×2

150

100 + 22 ×2

Open

3.3

45

92

10

5

5

2000

0.8

10 ×2

150

100 + 22 ×2

Open

5

45

90

10

5

5

2000

1

10 ×2

150

100 + 22 ×2

Open

3.3

55

109

10

5

5

2000

1

10 ×2

150

100 + 22 ×2

Open

5

55

105

10

5

5

2000

1.5

10 ×2

150

100 + 22 ×2

Open

3.3

80

157

10

5

5

2000

1.5

10 ×2

150

100 + 22 ×2

Open

5

80

156

10

5

5

2000

2.5

10 ×2

150

100 + 22 ×2

Open

3.3

120

239

15

5

5

2000

2.5

10 ×2

150

100 + 22 ×2

Open

5

120

241

15

5

5

2000

3.3

10 ×2

150

100 + 22 ×2

Open

5

120

291

15

5

5

2000

APPLICATIONS INFORMATION

Safety Considerations

The LTM4659 modules do not provide galvanic isolation

from VIN to VOUT. There is no internal fuse. If required,

a slow-blow fuse with a rating twice the maximum input

current must be provided to protect each unit from cata-

strophicfailure.Thedevicedoessupportthermalshutdown

and overcurrent protection.

Layout Checklist/Example

The high integration of LTM4659 makes the PCB board

layoutverysimpleandeasy.However,tooptimizeitselectri-

cal and thermal performance, some layout considerations

are still necessary.

• Use large PCB copper areas for high-current paths,

including VIN, GND and VOUT. It helps to minimize the

PCB conduction loss and thermal stress.

• Place high frequency ceramic input and output capaci-

tors next to the VIN, GND and VOUT pins as close as

possible to minimize high frequency noise.

• Place a dedicated power ground layer underneath

the unit.

• To minimize the via conduction loss and reduce module

thermal stress, use multiple vias for interconnection

between top layer and other power layers.

• Do not put via directly on the pad, unless they are

capped or plated over.

• Use a separated GND ground copper area for compo-

nents connected to signal pins. Connect the AGND to

GND underneath the unit.

• For parallel modules, tie the VOUT, RUN, and COMP

pins together. Use an internal layer to closely connect

these pins together.

• Bring out test points on the signal pins for monitoring.

Figure 15 shows a good example of the recommended

layout.