ADC3908CSSS datasheet(36/131 Pages) TI1

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6.3.6 Digital Features

6.3.6.1 Digital Down Converter

The ADC3910Dx and ADC3910Sx has an optional dual on-chip digital down converters (DDC) that can be

enabled via SPI register (0x0D4). It supports real decimation by 2, 4, 8, and 16. Real decimation operation is

illustrated with an example in Figure 6-9. The output data rate is decimated. A decimation of 8 results in an

output data rate FS,OUT = FS/8 with a Nyquist zone of FS/16.

FS/2

FS/4

FS/8

FS/16

FS/32

Decima on by 2

Decima on by 4

Decima on by 8

Decima on by

Input Signal

Figure 6-9. Real decimation illustration, default

6.3.6.1.1 Digital Down Converter Data Select

Each digital comparator has the capability of selecting either channel with or without decimation data via SPI

write (0x200, 0x203).

ADC A

ADC B

Digital Downconverter

Figure 6-10. Digital down converter data multiplexer

6.3.6.1.2 Decimation Filter

The ADC3910Dx and ADC3910Sx has a stop band rejection of at least 70dB, and a pass-band bandwidth of

approximately 80%. Table 6-2 gives an overview of the pass-band bandwidth of the different decimation settings

with respect to ADC sampling rate FS.

ADC3910D025, ADC3910D065, ADC3910D125

ADC3910S025, ADC3910S065, ADC3910S125

SBASAD1A – DECEMBER 2023 – REVISED MAY 2024

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ADC3908CSSS 数据表(PDF) 36 Page - Texas Instruments