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ADC3908CSSS 数据表(PDF) 4 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 4 Page - Texas Instruments |
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4 / 131 page ![]() Table 4-1. Pin Functions (continued) PIN TYPE DESCRIPTION NAME NO. D0 4 O CMOS digital lane output data. D1 3 O D2 2 O D3 1 O D4 32 O D5 31 O D6 26 O D7 25 O D8 24 O D9 23 O D10 22 O D11 21 O DCLK 30 O CMOS output for data bit clock. DCLK/FCLK 29 O Default is Inverse data bit clock for CMOS output data. Frame clock can be selected via SPI write OEN/PD 6 I Output data enable. This pin is active low with default 60kΩ pull-down. Can be configured as power down pin through SPI. POWER SUPPLY AVDD 12, 13 I Analog 1.8V power supply GND PowerPAD™ I Analog Ground, 0V IOVDD 27 I 1.8V to 3.3V power supply for digital interface DGND 28 I Ground, 0V for digital interface OTHER NC 17 N/A No connection. Connect to ground ADC3910D025, ADC3910D065, ADC3910D125 ADC3910S025, ADC3910S065, ADC3910S125 SBASAD1A – DECEMBER 2023 – REVISED MAY 2024 www.ti.com 4 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 |
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