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ADC3908CSSS 数据表(PDF) 13 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 13 Page - Texas Instruments |
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13 / 131 page  5.10 Timing Requirements (continued) Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages. Typical values are specified at TA = 25°C, ADC sampling rate = 125 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT tPD Propagation delay: sampling clock falling edge to output data delay Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge TS/4 + 3 ns Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge TS/4 + 3 tCD DCLK rising edge to output data delay 4 Lane serial CMOS Fout = 10 MSPS -7.25 -6.25 -5.25 ns Fout = 20 MSPS -4.125 -3.125 -2.125 Fout = 30 MSPS -3.08 -2.08 -1.08 DCLK rising edge to output data delay 2 Lane serial CMOS Fout = 5 MSPS -7.25 -6.25 -5.25 Fout = 10 MSPS -4.125 -3.125 -2.125 Fout = 15 MSPS -3.08 -2.08 -1.08 tDV Data valid, 4 Lane serial CMOS Fout = 10 MSPS -7.25 -6.25 -5.25 ns Fout = 20 MSPS -4.125 -3.125 -2.125 Fout = 30 MSPS -3.08 -2.08 -1.08 Data valid, 2 Lane serial CMOS Fout = 5 MSPS -7.25 -6.25 -5.25 Fout = 10 MSPS -4.125 -3.125 -2.125 Fout = 15 MSPS -3.08 -2.08 -1.08 SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input fCLK,SCLK Serial clock frequency 20 MHz tS,SEN SEN falling edge to SCLK rising edge 10 ns tH,SEN SCLK rising edge to SEN rising edge 10 tS,SDIO SDIO setup time from rising edge of SCLK 17 tH,SDIO SDIO hold time from rising edge of SCLK 9 SERIAL PROGRAMMING INTERFACE (SDIO) - Output tOZD Delay from falling edge of 8th SCLK cycle during read operation for SDIO transition from tri-state to valid data 3.9 10.8 ns tODZ Delay from SEN rising edge for SDIO transition from valid data to tri-state 3.4 14 tOD Delay from falling edge of 8th SCLK cycle during read operation to SDIO valid 3.9 10.8 (1) In low latency mode the default interface is DDR for dual channel devices and SDR for single channel devices. Other interface configurations such as serial CMOS will add additional latency. www.ti.com ADC3910D025, ADC3910D065, ADC3910D125 ADC3910S025, ADC3910S065, ADC3910S125 SBASAD1A – DECEMBER 2023 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 |
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