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ADC3908CSSS 数据表(PDF) 40 Page - Texas Instruments

部件名 ADC3908CSSS
功能描述  ADC3910Dx and ADC3910Sx 10-bit, 25 to 125MSPS Low Latency, Low Power, Small, Single and Dual Channel ADC with Integrated Input Buffers
PDF  131 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

ADC3908CSSS 数据表(HTML) 40 Page - Texas Instruments

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Table 6-3. Serial CMOS Lane Rate Examples with Real Decimation and 12/16-bit Output Resolution
Output
Resolution
Decimation
Lanes
Serialization
DCLK
DCLK Divider
FCLK
Register 0xA7
Register 0x200
Registers
0xAE...B3
Register 0xA6
Register 0xA8
Register 0x88
8 bits
Bypass
8
1
FS
/1
N/A
10 bits
10
1
FS
/1
N/A
12 bits
12
1
FS
/1
N/A
/2
12
1
FS / 2
/2
N/A
/4
12
1
FS / 4
/4
N/A
/8
12
1
FS / 8
/8
N/A
/16
12
1
FS /16
/16
N/A
16 bits
/2
8
2
FS
/2
FS / 2
/4
8
2
FS / 2
/4
FS / 2
4
4
FS
FS / 4
/8
8
2
FS / 4
/8
FS / 2
4
4
FS / 2
FS / 4
2
8
FS
FS / 8
/16
8
2
FS / 8
/16
FS / 2
4
4
FS / 4
FS / 4
2
8
FS / 2
FS / 8
Note
16 bit resolution does not support a serialization factor of 1.
B0
B1
B6
B7
B8
B9
B14
B15
DCLK
Sample N
D11
D05
D04
D10
A15
A14
A9
A8
A7
A6
A1
A0
DDR
DEFAULT
8 Lane
2x Serializa on
B8
B9
B14
B15
B0
B1
B6
B7
A0
A1
A6
A7
DCLK
Sample N
D11
D05
D04
D10
A15
A14
A9
A8
FCLK
DDR
8 Lane
2x Serializa on
B12
B15
B4
B5
A4
A7
B0
B2
A0
A3
B8
B8
A8
A11
Sample N
D11
D05
D02
D08
A15
A12
DCLK
HDDR
8 Lane
2x Serializa on
B12
B15
B4
B5
A4
A7
B0
B2
A0
A3
B8
B8
A8
A11
Sample N
D11
D07
D04
D08
A15
A12
DCLK
SDR
8 Lane
2x Serializa on
FCLK
FCLK
FCLK
Figure 6-21. 16 Bit, 8 Lanes, 2x Serialization
ADC3910D025, ADC3910D065, ADC3910D125
ADC3910S025, ADC3910S065, ADC3910S125
SBASAD1A – DECEMBER 2023 – REVISED MAY 2024
www.ti.com
40
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125



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