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ADC3908CSSS 数据表(PDF) 78 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 78 Page - Texas Instruments |
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78 / 131 page  Table 6-86. DEV_CFG_4 Register Field Descriptions (continued) Bit Field Type Reset Description 0 8BIT_EN R/W 0h ADC resolution 0b = 10-bit resolution 1b = 8-bit resolution 6.6.1.81 GBL_CLK_CFG_1 Register (Address = 484h) [Reset = 0h] Return to the Summary Table. Table 6-87. GBL_CLK_CFG_1 Register Field Descriptions Bit Field Type Reset Description 1 CLK_GBL R/W 0h Global clock enable. Controls clock for digital block 0b = Gates clock to digital 1b = Ungates clock to digital 0 RESERVED R 0h 6.6.1.82 GBL_CLK_CFG_2 Register (Address = 4BEh) [Reset = 00h] Return to the Summary Table. Table 6-88. GBL_CLK_CFG_2 Register Field Descriptions Bit Field Type Reset Description 7:6 CLK_STATS R/W 0h Controls clock to statistics engine 00b = Disables clock to statistics engine 11b = Enables clock to statistics engine 5:4 CLK_COMP R/W 0h Controls clock to comparator 00b = Disables clock to comparator 11b = Enables clock to comparator 3:2 CLK_DEC R/W 0h Controls clock to decimation 00b = Disables clock to decimation 11b = Enables clock to decimation 1:0 CLK_CC R/W 0h Controls clock to channel corrections 00b = Disables clock to channel corrections 11b = Enables clock to channel corrections 6.6.1.83 GBL_CLK_CFG_3 Register (Address = 4BFh) [Reset = 0h] Return to the Summary Table. Table 6-89. GBL_CLK_CFG_3 Register Field Descriptions Bit Field Type Reset Description 1:0 CLK_OUT R/W 0h Controls clock to digital output block 00b = Disables clock to digital output 11b = Enables clock to digital output ADC3910D025, ADC3910D065, ADC3910D125 ADC3910S025, ADC3910S065, ADC3910S125 SBASAD1A – DECEMBER 2023 – REVISED MAY 2024 www.ti.com 78 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 |
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