ADC3908CSSS datasheet(50/131 Pages) TI1

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6.5 Programming

The device is primarily configured and controlled using the serial programming interface (SPI). After initial power

up, the default operating configuration is shown in Table 6-4.

Table 6-4. Default device configuration after power up

FEATURE

DEFAULT

Signal Input

Differential

Reference

Internal

Channel Corrections

Disabled

Decimation

Disabled

Comparators

Disabled

Statistics Engine

Disabled

Interface

DDR, 10 lanes

Output Format

Two's Complement

6.5.1 Configuration using the SPI interface

The device has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial

interface enable), SCLK (serial interface clock) and SDIO (serial interface data input/output) pins. Serially shifting

bits into the device is enabled when SEN is low. Serial data input are latched at every SCLK rising edge when

SEN is active (low). The serial data are loaded into the register at every 16th SCLK rising edge when SEN is low.

When the word length exceeds a multiple of 16bits, the excess bits are ignored. Data can be loaded in multiples

of 16-bit words within a single active SEN pulse. The interface can function with SCLK frequencies from 20MHz

down to low speeds (of a few hertz) and also with a non-50% SCLK duty cycle.

6.5.1.1 Register Write

The internal registers can be programmed following these steps:

1. Drive the SEN pin low

2. Set the R/W bit to 0.

3. Initiate a serial interface cycle by specifying the address of the register (A[14:0]) whose content is written

4. Write the 8-bit data that are latched in on the SCLK rising edges

Figure 6-33 show the timing requirements for the serial register write operation.

tSCLK

tS,SDIO

tH,SDIO

tH,SEN

A12

A11

A10

A14

A13

SDATA

SCLK

SEN

tS,SEN

R/W

Figure 6-33. Serial Register Write Timing Diagram

ADC3910D025, ADC3910D065, ADC3910D125

ADC3910S025, ADC3910S065, ADC3910S125

SBASAD1A – DECEMBER 2023 – REVISED MAY 2024

www.ti.com

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