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ADC3908CSSS 数据表(PDF) 55 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 55 Page - Texas Instruments |
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55 / 131 page  Table 6-10. INTERLEAVE Register Field Descriptions Bit Field Type Reset Description 2 INTERLEAVE R/W 0h Enables interleaving mode where channels A and B are both sampling channel A input and channel B clock is 180 degrees out of phase with respect to channel A to achieve a 2x sampling rate. Only applies to dual channel devices. 0b = Interleaving mode disabled 1b = Interleaving mode enabled 1:0 RESERVED R 0h 6.6.1.5 REF_EQ Register (Address = 85h) [Reset = 00h] Return to the Summary Table. Table 6-11. REF_EQ Register Field Descriptions Bit Field Type Reset Description 6 REF_EQ R/W 0h Enable when using external reference to improve temperature tracking. Internal bandgap is expected to have 7 mV of variation across the device operating temperature. 0b = Reference equalization disabled 1b = Reference equalization enabled 5:0 RESERVED R 0h 6.6.1.6 CLK_RESET Register (Address = 87h) [Reset = 00h] Return to the Summary Table. Table 6-12. CLK_RESET Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0h Reserved 6 RESERVED R 0h Reserved 5:0 RESERVED R 0h 6.6.1.7 DEV_CFG_1 Register (Address = 88h) [Reset = 00h] Return to the Summary Table. Table 6-13. DEV_CFG_1 Register Field Descriptions Bit Field Type Reset Description 7 FCLK_EN R/W 0h Enables frame clock output on DCLKZ pin. Must be enabled in Serial CMOS mode. 0b = Frame clock output on DCLKZ pin disabled 1b = Frame clock output on DCLKZ pin enabled 6 CNL_PDN R/W 0h Powers down internal non-linearity correction. Useful for input frequencies above 100 MHz and reduces current by 0.5 mA. 0b = Non-linearity correction enabled 1b = Non-linearity correction powered down 5 BUF_CHB R/W 0h Reduces current to ADC channel B input buffer which reduces buffer bandwidth. Recommended for input signals below 25 MHz and reduces current consumption by 2 mA. 0b = Input buffer full power mode 1b = Input buffer low power mode 4 BUF_CHA R/W 0h Reduces current to ADC channel A input buffer which reduces buffer bandwidth. Recommended for input signals below 25 MHz. Reduces current consumption by 2 mA. 0b = Input buffer full power mode 1b = Input buffer low power mode www.ti.com ADC3910D025, ADC3910D065, ADC3910D125 ADC3910S025, ADC3910S065, ADC3910S125 SBASAD1A – DECEMBER 2023 – REVISED MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 55 Product Folder Links: ADC3910D025 ADC3910D065 ADC3910D125 ADC3910S025 ADC3910S065 ADC3910S125 |
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