STR910FAM32X6 datasheet(20/78 Pages) STMICROELECTRONICS

20 / 78 page

Functional overview

STR91xFA

20/78

peripheral clock from the APB, and an 8-bit clock pre-scaler is available. When enabled by

firmware as a watchdog, this timer will cause a system reset if firmware fails to periodically

reload this timer before the terminal count of 0x0000 occurs, ensuring firmware sanity. The

watchdog function is off by default after a reset and must be enabled by firmware.

2.13.4 External RESET_INn pin

This input signal is active-low with hystereses (VRHYS). Other open-drain, active-low system

reset signals on the circuit board (such as closure to ground from a push-button) may be

connected directly to the RESET_INn pin, but an external pull-up resistor to VDDQ must be

present as there is no internal pullup on the RESET_INn pin.

A valid active-low input signal of tRINMIN duration on the RESET_INn pin will cause a system

reset within the STR91xFA. There is also a RESET_OUTn pin on the STR91xFA that can drive

other system components on the circuit board. RESET_OUTn is active-low and has the same

timing of the Power-On-Reset (POR) shown next, tPOR.

2.13.5 Power-up

The LVD circuitry will always generate a global reset when the STR91xFA powers up, meaning

internal reset is active until VDDQ and VDD are both above the LVD thresholds. This POR

condition has a duration of tPOR, after which the CPU will fetch its first instruction from address

0x0000.0000 in Flash memory. It is not possible for the CPU to boot from any other source

other than Flash memory.

2.13.6 JTAG debug command

When the STR91xFA is in JTAG debug mode, an external device which controls the JTAG

interface can command a system reset to the STR91xFA over the JTAG channel.

2.13.7 Tamper detection

On 128-pin and 144-ball STR91xFA devices only, there is a tamper detect input pin,

TAMPER_IN, used to detect and record the time of a tamper event on the end product such as

malicious opening of an enclosure, unwanted opening of a panel, etc. The activation mode of

the tamper pin is programmable to one of two modes. One is Normally Closed/Tamper Open,

the other mode will detect when a signal on the tamper input pin is driven from low-to-high, or

high-to-low depending on firmware configuration. Once a tamper event occurs, the RTC time

(millisecond resolution) and the date are recorded in the RTC unit. Simultaneously, the SRAM

standby voltage source will be cut off to invalidate all SRAM contents. Tamper detection control

and status logic are part of the RTC unit.

2.14

Real-time clock (RTC)

The RTC combines the functions of a complete time-of-day clock (millisecond resolution) with

an alarm programmable up to one month, a 9999-year calender with leap-year support,

periodic interrupt generation from 1 to 512 Hz, tamper detection (described in Section 2.13.7),

and an optional clock calibration output on the JRTCK pin. The time is in 24 hour mode, and

time/calendar values are stored in binary-coded decimal format.

The RTC also provides a self-isolation mode that is automatically activated during power down.

This feature allows the RTC to continue operation when VDDQ and VDD are absent, as long as

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