STR910FAM32X6 datasheet(30/78 Pages) STMICROELECTRONICS

30 / 78 page

Functional overview

STR91xFA

30/78

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One pulse generation in response to an external event

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A dedicated interrupt to the CPU with five interrupt flags

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The OCF1 flag (Output Compare 1) from the timer can be configured to trigger an ADC

conversion

2.25.1 DMA

A programmable DMA channel may be assigned by CPU firmware to service each timer/

counter module TIM0 and TIM1 for fast and direct single transfers.

2.26

Three-phase induction motor controller (IMC)

The STR91xFA provides an integrated controller for variable speed motor control applications.

Six PWM outputs are generated on high current drive pins P6.0 to P6.5 for controlling a three-

phase AC induction motor drive circuit assembly. Rotor speed feedback is provided by

capturing a tachometer input signal on pin P6.6, and an asynchronous hardware emergency

stop input is available on pin P6.7 to stop the motor immediately if needed, independently of

firmware.

The IMC unit has the following features:

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Three PWM outputs generated using a 10 or 16-bit PWM counter, one for each phase U,

V, W. Complimentary PWM outputs are also generated for each phase.

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Choice of classic or zero-centered PWM generation modes

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10 or 16-bit PWM counter clock is supplied through a programmable 8-bit prescaler of the

APB clock.

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Programmable 6 or 10-bit dead-time generator to add delay to each of the three

complimentary PWM outputs

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8-bit repetition counter

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Automatic rotor speed measurement with 16-bit resolution. Schmitt trigger tachometer

input with programmable edge detection

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Hardware asynchronous emergency stop input

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A dedicated interrupt to CPU with eight flags

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Enhanced Motor stop output polarity configuration

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Double update option when PWM counter reaches the max and min values in Zero-

centered mode

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Locking feature to prevent some control register bits from being advertently modified

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Trigger output to start an ADC conversion

2.27

External memory interface (EMI)

STR91xFA devices in 128-pin and 144-ball packages offer an external memory bus for

connecting external parallel peripherals and memories. The EMI bus resides on ports 7, 8, and

9 and operates with either an 8 or 16-bit data path. The configuration of 8 or 16 bit mode is

specified by CPU firmware writing to configuration registers at run-time. If the application does

not use the EMI bus, then these port pins may be used for general purpose I/O as shown in

Table 5.

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