STPM01 datasheet(24/56 Pages) STMICROELECTRONICS

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Theory of operation

STPM01

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The detected tamper condition is stored in the BIT status bit. If BIT=0 tamper is not

detected, if BIT=1 a tamper condition has been detected. In standalone mode the BIT flag is

also available in the SDATD pin.

When internal signals are not good enough to perform the computation, i.e. line period is out

or range or

∑∆ signals from analog part are stacked at high or low logic level, or no load

condition is activated, the tamper module is disabled and its state is preset to normal.

8.11

Phase compensation

The STPM01 is does not introduce any phase shift between voltage and current channel.

However, the voltage and current signals come from transducers, which could have inherent

phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current

transformer (CT). These phase errors can vary from part to part, and they must be corrected

in order to perform accurate power calculations. The errors associated with phase mismatch

are particularly noticeable at low power factors. The STPM01 provides a means of digitally

calibrating these small phase errors through a introducing delays on the voltage or current

signal. The amount of phase compensation can be set using the 4 bits of the phase

calibration register (CPH).

The default value of this register is at value of 0 which gives 0° phase compensation. When

the 4 bits give a CPH of 15 (1111) the introduced compensation is +0.576°. This

compensates the phase shift usually introduced by the current sensor, while the voltage

sensor, normally a resistor divider, does not introduce any delay. The resolution step of the

phase compensation is 0.038°.

8.12

Clock generator

All the internal timing of the STPM01 is based on the CLKOUT signal. This signal can be

generated in three different ways:

1. RC: this oscillator mode can be selected using the RC configuration bit. If RC=1 the

STPM01 will run using the RC oscillator. A resistor connected between CLKIN and

Ground will set the RC current. For 4Mhz operation the suggested settling resistor is

12k

Ω; The oscillator frequency can be compensated using the CRC configuration bit

(see table 13)

2. Quartz: If RC=0 the oscillator will work with an external crystal. The suggested circuit

is depicted in fig. 18;

3. External Clock: keeping RC=0, it is also possible to feed the CLKOUT pin with an

external oscillator signal

The clock generator is powered from analog supply and is responsible for two tasks. The

first one is to retard the turn on of some function blocks after POR in order to help smooth

start of external power supply circuitry by keeping off all major loads.

The second task of the clock generator is to provide all necessary clocks for analog and

digital parts. Within this task, the MDIV configuration bit is used to inform the device about

the nominal frequency value of CLKOUT. Two nominal frequency ranges are expected, from

4.000MHz to 4.194MHz (MDIV=0) or from 8.000MHz to 8.192MHz (MDIV=1).

STPM01 数据表(PDF) 24 Page - STMicroelectronics

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