STPM01 datasheet(31/56 Pages) STMICROELECTRONICS

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STPM01

Theory of operation

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retain 56 bits of information even if it has been unsupplied for an undefined time. That’s why

the CFG signals are used to keep certain configuration and calibration values of device.

The very first CFG bit, called TSTD, is used to disable any change of system signals after it

was permanently set. During the configuration phase, each bit set to logic level 1 will

increase the supply current of STPM01 of about 120 µA, until the TSTD bit is set to 1. The

residual increase of supply current is 2µA per each bit set to 1. It is then recommended to

set the TSTD bit to 1 after the configuration procedure in order to keep the supply current as

low as possible.

The STPM01 can work either using the data stored in the OTP cells either the data available

in the shadow latches. This can be chosen according to the value RD Mode signal (see

Mode Signal paragraph for description). If the RD is set, the CFG bits originates from

corresponding OTP shadow latches otherwise, if the RD is cleared, the CFG bits originates

from corresponding OTP antifuses. This way one can temporary sets up certain

configuration or calibration of device then verify it and then change it, if it is necessary. For

example, this is extensively exercised during production tests.

Each configuration bit can be written sending a byte command to STPM01 through its SPI

interface. The procedure to write the configuration bits is described in the SPI section.

After the TSTD bit has been set, the only write commands accepted will be the Precharge

and the Remote Reset, this implies that the shadow latches cannot be used as source of

configuration data anymore.

Table 16.

Configuration bits map

Address

Name

N. of

bits

Description (1)

6-BIT

Binary

DEC

000000

TSTD

Test mode and OTP write disable:

- TSTD=0: testing and continuous pre-charge of OTP when in read mode,

- TSTD=1:normal operation and no more writes to OTP

000001

MDIV

Measurement frequency range selection:

- MDIV=0: 4.000MHz to 4.194MHz,

- MDIV=1: 8.000MHz to 8.192MHz

000010

Type of internal oscillator selection:

- RC=0:crystal oscillator,

- RC=1:RC oscillator

000011

APL

Peripheral or Standalone mode:

- APL=0: peripheral, MON=WatchDOG; MOP=ZCR, LED=pulses,

- APL=1: peripheral, MOP=

∆Σ Voltage; MON=∆Σ current; LED=Mux (current) -

APL=2: standalone, MOP,MON=stepper, LED=pulses, SCLNLC=no load

condition, SDATD=tamper detected, SYN=negative active power direction

- APL=3: standalone, MOP:MON=stepper, LED=pulses according to KMOT,

SCLNLC=no load condition, SDATD=tamper detected, SYN=negative active

power direction

000100

4 (1)

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