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STPM01 数据表(PDF) 37 Page - STMicroelectronics |
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STPM01 数据表(HTML) 37 Page - STMicroelectronics |
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37 / 56 page ![]() STPM01 Theory of operation 37/56 8.21.1 Remote Reset The timing diagram of the operation is shown on the Figure 1. The time step can be as short as 30ns. The internal reset signal is named RRR. Unlike the POR, the RRR signal does not cause the 30ms retard restart of analog module and the 120ms retard restart of digital module. This signal doesn’t clear the mode signals. All the time intervals must be longer than 30ns. t7 Æ t8 is the reset time, this interval must be longer than 30ns as well. 8.22 Reading data records Data records reading will take place most often when there will be an on-board microcontroller in an application. Such microcontroller will be able to read all measurement results and all system signals (configuration, calibration, status, mode). Again, the time step can be as short as 30ns. There are two phases of reading, called latching and shifting. Latching is used to sample results into transmission latches. The transmission latches are the Flip-Flops that hold the data in the SPI interface. This is done with the active pulse on SYN when SCS is idle. The length of pulse on SYN must be longer than 2 periods of measurement clock, i.e. more than 500ns at 4MHz. The shifting starts when SCS become active. In the beginning of this phase another, but much shorter pulse (30ns) on SYN should be applied in order to ensure that an internal transmission serial clock counter is reset to zero. An alternative way is to extend the pulse on SYN into the second phase of reading. After that reset is done, a 32 serial clocks per data record should be applied. Up to 8 data records can be read this way. This procedure can be aborted at any time by deactivation of SCS (see figure 23). The first read out byte of data record is Least Significant Byte (LSB) of data value and of course, the fourth byte is Most Significant Byte (MSB) of data value. Each byte can be Figure 23. Timing for providing remote reset request t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 t 9 t 10 SCS SYN SCLNLC SDATD SCS SYN SCLNLC SDATD |
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