STPM01 datasheet(41/56 Pages) STMICROELECTRONICS

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STPM01

Theory of operation

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state buffer could be omitted by an emulation of SPI just to send some command. On a

microcontroller this would be done by the following steps:

1. disable the SPI module;

2. set SDI pin which is connected to SDATD to be output;

3. activate SYN first and then SCS;

4. apply new bit value to SDI and activate SCL;

5. deactivate SCL;

6. repeat the last two steps seven times to complete one byte transfer;

7. repeat the last three steps for any remaining byte transfer;

8. set SDI pin to be input;

9. deactivate SCS and the SYN;

10. enable the SPI module;

In case of Precharge command (0xFF), emulation above is not necessary. Due to the pull up

device on the SDATD pin of the STPM01 the processor needs to perform the following

steps:

1. activate SYN first in order to latch the results;

2. after at least 1µs activate SCS;

3. write one byte to the transmitter of SPI (this will produce 8 pulses on SCL with

SDI=1);

4. deactivate SYN;

5. optionally read the data records (the sequence of reading will be altered;

6. deactivate SCS;

Permanent writing of the CFG bits

In order to make a permanent set of some CFG bits, the following procedure should be

conducted:

1. collect all addresses of CFG bits to be permanently set into some list;

2. clear all OTP shadow latches;

3. set the system signal RD;

4. connect a current source of at least +14V, 1mA to 3mA to VOTP;

5. wait for VOTP voltage is stable;

6. set one OTP shadow latch from the list;

7. set the system signal WE;

8. wait for 300µs;

9. clear the system signal WE;

10. clear the OTP shadow latch which was set in step 6;

11. until all wanted CFG bits are permanently set, repeat steps 5 to 11;

12. disconnect the current source;

13. wait for VOTP voltage is less than 3V;

14. clear the system signal RD;

15. read all data records, in the last two of them there is read back of CFG bits;

16. if verification of CFG bits fails and there is still chance to pass, repeat steps 1

to 16.

For steps of set or clear apply the timing shown in Figure 24 with proper signal on the

SDATD. For step 15 apply the timing shown in Figure 23.

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