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ICS1893CFILF 数据表(PDF) 80 Page - Integrated Circuit Systems |
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ICS1893CFILF 数据表(HTML) 80 Page - Integrated Circuit Systems |
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80 / 126 page  ICS1893CF, Rev. F, 03/01/07 Mar. 2007 80 Chapter 7 Management Register Set ICS1893CF Data Sheet - Release Copyright © 2007, Integrated Device Technology, Inc. All rights reserved. 7.14 Register 19: Extended Control Register 2 The Extended Control Register provides more refined control of the internal ICS1893CF operations. Note: 1. For an explanation of acronyms used in Table 7-20, see Chapter 1, “Abbreviations and Acronyms”. 2. During any write operation to any bit in this register, the STA must write the default value to all Reserved bits. † The default is the state of this pin at reset. Table 7-21. Extended Control Register (register [0x13]) Bit Definition When Bit = 0 When Bit = 1 Ac- cess SF De- fault Hex 19.15 Node Mode Node mode Repeater mode RO – 0 4 19.14 Hardware/Software Mode Hardware mode Software mode RO – 1 19.13 Remote Fault No faults detected Remote fault detected RO – 0 19.12 ICS reserved Read unspecified Read unspecified RW – 0 19.11 ICS reserved Read unspecified Read unspecified RW – 0 2 19.10 ICS reserved Read unspecified Read unspecified RO – 0 19.9 AMDIX_EN See Table 7-22 See Table 7-22 RW – 1 19.8 MDI_MODE See Table 7-22 See Table 7-22 RW – 0 19.7 Twisted Pair Tri-State Enable, TPTRI Twisted Pair Signals are not Tri-Stated or No effect Twisted Pair Signals are Tri-Stated RW – 0 0 19.6 ICS reserved Read unspecified Read unspecified RW – 0 19.5 ICS reserved Read unspecified Read unspecified RW – 0 19.4 ICS reserved Read unspecified Read unspecified RW – 0 19.3 ICS reserved Read unspecified Read unspecified RW – 0 1 19.2 ICS reserved Read unspecified Read unspecified RW – 0 19.1 ICS reserved Read unspecified Read unspecified RW – 0 19.0 Automatic 100Base-TX Power Down Do not automatically power down Power down automatically RW – 1 |
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