TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

1

POST OFFICE BOX 655303

Physical-Layer (PHY) Interface for

Full-Duplex or Half-Duplex Connection to

10BASE-T, 100BASE-TX, and 100BASE-FX

Networks

Power-Down Capability for CardBus and

Other Applications Requiring Low Power

Equalization Provide for Minimal External

Component Count to Reduce System Cost

Supported With Magnetics Package and

RJ-45 Connector

Model (HBM) Protection 1.5 kV Per JEDEC

JESD 22-A114-A

Digital Phase-Locked Loop (PLL)

Technology Allows Data Recovery at

10 Mbit/s and 100 Mbit/s, Requiring One

20-MHz Clock Reference Source

– Fully Compliant With IEEE Std 802.3

– Smart Squelch for Improved Noise

Immunity

– Integrated Transmit Wave Shaping

– Autopolarity (Reverse-Polarity

Correction)

– Transmit Jabber Detection

– Fully Compliant With ANSI Twisted-Pair

Physical-Media-Dependent (TP-PMD)

Standard and IEEE Std 802.3

– Synthesized Rise-Time Control

– Integrated Receiver With Adaptive Line

Equalization (EQ) and Baseline Wander

(BLW) Correction (DC Restoration)

Media-Independent Interface (MII) That

Includes Management Interface

(N-Way) With Next-Page Support

(TAP)

Flatpack

RJ-45

Magnetics

MII

MII

Management

Registers

MII Data

and

Control

Interface

JTAG

PLL Clock

Generation

and Recovery

Autonegotiation

With Next-Page

Support

– BLW Correct

– Adaptive EQ

– MLT-3

10/100 PMD

10BASE-T

PCS and PMA

100BASE-TX

Physical Coding Sublayer

(PCS) and

Physical Medium Attachment

(PMA)

10/100 MAC

Figure 1. 10BASE-T/100BASE-TX PHY

Copyright

© 1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

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