TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

27

POST OFFICE BOX 655303

autonegotiation next-page transmit register – AN_np at 0x07

BIT

15

14

13

12

11

10

987654321

BIT

0

NP

ACK

MP

ACK2

T

Message or Unformatted Code Field

Figure 16. Autonegotiation Next-Page Transmit Register

Table 14. Autonegotiation Next-Page Transmit-Register Bit Functions

BIT

FUNCTION

NAME

NO.

FUNCTION

NP

15

Next page. When a next page with NP set to 1 is transmitted, the link partner is informed that another next page

is to be transmitted (see Table 11). The default value of NP is 0.

ACK

14

Acknowledge. Reserved for internal use of the autonegotiation process. Write as 0, ignore during read.

MP

13

Message page. When MP is set to 1, AN_np contains a message-page code field. When MP is cleared to 0, AN_np

contains an unformatted-page code field (see Table 11). The default value of MP is 1.

ACK2

12

Acknowledge 2. Reserved for internal use of the autonegotiation process. Write as 0, ignore during read.

T

11

Toggle. Reserved for internal use of the autonegotiation process. Write as 0, ignore during read.

Message or

Unformatted

Code Field

10–0

Message or unformatted code field (see Table 11). The default value of the code field is 000.0000.0001, the null

message code.

PHY identifier high/low – TXPHY_id at 0x10

This hardwired 16-bit register contains a TI-assigned identifier code for the PHY PMIs. An additional identifier

is required to identify non-IEEE Std 802.3 PHY/PMIs, which are not otherwise supported by the IEEE Std 802.3

MII specification. The identifier code for the internal 10BASE-T/100BASE-TX PHY is 0x0003.

PHY control register – TXPHY_ctl at 0x11

BIT

15

14

13

12

11

10

987654321

BIT

0

I

G

L

I

N

K

S

W

A

P

O

L

M

A

N

C

O

N

F

S

Q

E

E

N

M

T

E

S

T

F

I

B

E

R

F

E

F

E

N

N

O

E

N

D

E

C

N

O

A

L

I

G

N

D

U

P

O

N

L

Y

R

E

P

E

A

T

E

R

R

X

R

E

S

E

T

N

O

L

I

N

K

P

N

F

E

W

I

N

T

E

N

T

I

N

T

Figure 17. PHY Control Register

Table 15. PHY Control-Register Bit Functions

BIT

FUNCTION

NAME

NO.

FUNCTION

IGLINK

15

Ignore link. When IGLINK is cleared to 0 (default), the 10BASE-T PHY expects to receive link pulses from the link

partner (hub, switch, and so on) and clears the LINK bit in the GEN_sts register to 0 if they are not present. When

IGLINK is set to 1, the internal link-integrity-test state machine is forced to stay in the LINK GOOD state even when

no link pulses are being received, and it also causes the LINK bit to stay set to 1.

SWAPOL

14

Swap polarity. Allows swapping the receive polarity when the MANCONF bit is set to 1. Writing a 1 to SWAPOL causes

the PHY to use the reverse of the IEEE Std 802.3 standard polarity for the ARCVP/ARCVN 10BASE-T receiver-input

pair. This is used to compensate for a cable in which the receive pair has been wired incorrectly.

See the PLOK bit description in register 0

×12 for a detailed explanation.