TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

29

POST OFFICE BOX 655303

PHY status register – TXPHY_sts at 0x12

BIT

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BIT

0

MINT

PHOK

PLOK

TPENERGY

SYNCLOSS

FEFI

Reserved

Figure 18. PHY Status Register

Table 16. PHY Status-Register Bit Functions

BIT

FUNCTION

NAME

NO.

FUNCTION

MINT†

15

MII Interrupt. MINT indicates an MII-interrupt condition. The MII-interrupt request is activated and latched until this

register is read. Writing to MINT has no effect. MINT is set to 1 when:

– JABBER (register 0x0, bit 1) is set to 1.

– LINK (register 0x0, bit 2) changes state or is different from either the last read value or the current state of the link.

– RFAULT (register 0x1, bit 4) is set to 1.

– AUTOCMPLT (register 0x1, bit 5) is set to 1.

– PAGERX (register 0x6, bit 1) is set to 1.

– FEFI (register 0x12, bit 10) is set to 1.

– SYNCLOSS (register 0x12, bit 11) is set to 1.

– PHOK (register 0x12, bit 14) is set to 1.

Additional interrupt sources are active only when the MANCONF bit (register 0x11, bit 13) is set to 1. MINT is set

to a 1 when:

– TPENERGY (register 0x12, bit 12) is set to 1.

– PLOK (register 0x12, bit 13) changes state.

PHOK

14

Power high OK. When PHOK is set to 1, it indicates that the oscillator circuit connected to XTAL1 has begun to

oscillate (and perform around 75 cycles). PHY-sourced clocks (MRCLK and MTCLK) are not valid until PHOK is

asserted. The clocks can take up to 50 ms to become stable and the PHY requires the RESET bit to be set to make

certain it is in a valid state. When PHOK is 0, the PHY is not in a fully operational state.

PLOK

13

Polarity OK. PLOK set to a 1 (default) signifies that the 10BASE-T PHY is receiving valid (noninverted) link pulses.

PLOK always is set to a 1 when MANCONF is set to a 0, since the PHY automatically corrects polarity. If MANCONF

is set to a 1 for manual polarity configuration, PLOK is cleared to a 0 if a sequence of seven consecutive inverted

link pulses is detected. PLOK can be set to a 1 again only if the SWAPOL bit is toggled and then 1 noninverted link

pulse is received.

If MANCONF is a 1 and then cleared to a 0 when PLOK is still a 0, PLOK is not set to a 1 until SWAPOL is toggled.

This reenables the autopolarity detection and PLOK remains a 1.

10BASE-T polarity is determined strictly from link pulses and not from received data or TP idles.

TPENERGY

12

Twisted-pair energy detect. When TPENERGY is set to 1, it indicates that the PHY is receiving impulses on

ARCVP/ARCVN.

SYNCLOSS

11

100BASE-TX receive descrambler synchronization loss. The 100BASE-TX descrambler expects to receive at least

12 consecutive IDLE symbols every 722

µs. If these are not seen, then SYNCLOSS is set to 1, and the descrambler

attempts to resynchronize itself to the incoming scrambled data stream. The value of SYNCLOSS is latched high

until this register is read.

FEFI

10

Far-end fault indication. When enabled via the FEFEN bit in TXPHY_ctl, this bit is set to 1 if the FEFI signaling

sequence is being transmitted by the link partner. The value of FEFI is latched (held) high until this register is read.

Reserved

9–0

Reserved. Read and write as 0.

† Useful for switching applications (TI patented)