TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

17

POST OFFICE BOX 655303

MII interrupt operation

The TNETE2101 can provide an interrupt based on certain PHY events through the MII MDIO signal. This allows

software to receive an interrupt on events, such as a change in link, without periodically polling the device.

Interrupt is indicated by driving the MDIO terminal low after the quiescent cycle and while MDCLK is high. The

quiescent cycle is the cycle following the data transfer, during which neither the MACs nor the PHYs drive

the MDIO.

The interrupt feature is controlled by register bits, MINT, INTEN, and TINT. MINT is the MII-interrupt bit

(register 0x12, bit 15) and is set to a 1 when one or more interrupt events have occurred. INTEN is the

interrupt-enable bit (register 0x11, bit 1) which allows MINT to generate an interrupt on the MDIO terminal.

Additionally, to test interrupt operation (TINT), test interrupt (register 0x11, bit 0) can be set to a 1 which

generates an interrupt, regardless of the value of MINT and INTEN.

Once an interrupt has occurred, MINT can be set to a 0 again by reading the register that contains the event

status. Table 5 shows all the events that can cause MINT to be set and the register location.

Table 5. Interrupt Causes and Register Location

EVENT

CAUSE

REGISTER

BIT

JABBER

When set to a 1

0x01

1

LINK

Change in state or is different from either the last read value of current state of LINK

0x01

2

RFAULT

When set to a 1

0x01

4

AUTOCMPLT

When set to a 1

0x01

5

PAGERX

When set to a 1

0x06

1

FEFI

When set to a 1

0x12

10

SYNCLOSS

When set to a 1

0x12

11

TPENERGY

When set to a 1 and MANCONF is enabled

0x12

12

PLOK

Change in state and MANCONF is enabled

0x12

13

PHOK

When set to a 1

0x12

14

details of an interrupt on MDIO

machine. (After the first MII frame, the TNETE2101 does not require the 32 contiguous 1s before the start

of frame for synchronization.)

allows the device driving MDIO to set its output to a high-impedance state. After reaching the

high-impedance state, MDIO goes high due to the required external pullup on the MDIO signal.

the clock is held high, if an interrupt occurs, MDIO is driven low. The interrupt occurring is not contingent

on seeing another rising edge on the MDCLK, instead, it is clocked through, based on the internal PHY

clock.

a low, signifying the start of frame. If the MDIO line is high, there is no start of frame and the PHY again drives

the MDIO line low, if there is an interrupt. If start of frame is recognized, the PHY inhibits driving the interrupt

onto the MDIO line until after the MII frame has completed.