TNETE2101

10BASE-T/100BASE-TX/100BASE-FX

LOW-POWER PHYSICAL-LAYER INTERFACE

SPWS032D – JANUARY 1997 – REVISED MARCH 1999

12

POST OFFICE BOX 655303

100BASE-FX differential PECL interface

The PHY provides three pairs of differential PECL terminals for connection to external fiber-optic transceivers.

The data streams are 125-Mbit/s NRZI encoded, with the receive data stream routed to the digital PLL for data

recovery. To maintain a reliable lock on the digital PLL, the receive data stream must be jitter free.

The FSDP/FSDN serial data-detect pair must be differentially positive to enable data recovery. While this pair

is differentially negative, MRCLK is inactive, and no attempt is made to process any receive data appearing on

FRCVP/FRCVN.

Differential PECL signals should be terminated with a standard emitter-coupled logic (ECL) load of 50

Ω to a

reset and power up timing

At initial power up, the PHY performs an internal reset. No external reset circuitry is required; however, operation

During operation, a full reset of the device can be performed by taking MRST low for not less than 50

ms. Correct

operation of the device is not certain until 50 ms after MRST is deasserted high.

10BASE-T/100BASE-TX PHY operation

PHY link establishment

The PHY implements the full autonegotiation standard, including next-page capability. CAUTONEG, CSPEED,

and CDUPLEX are used to directly configure the link speed or to set and report autonegotiated speeds.

When CAUTONEG is deasserted low, CSPEED and CDUPLEX determine the link configuration. CSPEED and

CDUPLEX have weak pullups, giving a default configuration of full-duplex 100BASE-TX when not connected.

The rising edge of CAUTONEG latches the values of CSPEED and CDUPLEX into the autonegotiation

advertisement (AN_adv) register as shown in Table 1. This advertises to the link partner during negotiation of

the capabilities of PHY and the highest common link is determined. CSPEED and CDUPLEX then are driven

with the negotiated speed and duplex.

Table 1. External-Link Configuration Speeds

CSPEED

CDUPLEX

AN_adv

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0

0

0x0021

Half-duplex 10BASE-T

0

1

0x0061

Half-/full-duplex 10BASE-T

1

0

0x00A1

Half-duplex 10BASE-T

Half-duplex 100BASE-TX

1

1

0x00E1

Half-/full-duplex 10BASE-T

Half-/full-duplex 100BASE-TX

For external controlling and reading of CAUTONEG, CSPEED, and CDUPLEX, timing to be considered is

shown in Figure 3. CSPEED and CDUPLEX must not be driven externally for 1200 ms (maximum) after

CAUTONEG is asserted high. The PHY begins negotiation when CAUTONEG is asserted. In the final 750 ms

(minimum) of autonegotiation, the PHY drives CSPEED and CDUPLEX to indicate the link configuration. The

values of these two terminals can be latched on the rising edge of SLINK.