LP3950SL datasheet(20/31 Pages) NSC

20 / 31 page

Audio Synchronization (Continued)

INPUT BUFFERING

Figure 16 describes the LP3950 audio input buffering struc-

ture in high level. The electric parameters of the buffers are

described in Table Audio Synchronization Characteristics.

Operational amplifiers for both buffers are rail-to-rail input

opamps. The single ended buffer is simply a voltage follower.

DC level of the input signal is generated by a resistor divider.

The differential amplifier is a basic differential-to-single-

ended converter.

AUDIO SYNCHRONIZATION SIGNAL PATH

LP3950 audio synchronization is mainly done digitally and it

consists of following signal path blocks (see Figure 17)

•

Input buffers

•

Multiplexer

•

AD converter

•

DC remover

•

Automatic gain control (AGC) / programmable gain

•

3 band digital filter

•

Peak detector

•

Look-up tables (LUT)

•

Mode selector

•

Integrators

•

PWM generator

The digitized input signal has a DC component that is re-

moved by the digital DC REMOVER (-3 dB @

A400 Hz). The

automatic GAIN CONTROL adjusts the input signal to suit-

able range automatically. User can disable AGC and the gain

can be set manually with PROGRAMMABLE GAIN. The

LP3950 has two audio synchronization modes: amplitude

and frequency. For amplitude based synchronization the

PEAK DETECTION method is used. For frequency based

synchronization the three-way crossover FILTER separates

high pass, low pass and band pass signals. For both modes,

a predefined lookup table (LUT) is used to match the audio

visual effect. The MODE SELECTOR selects the synchroni-

zation mode. Reaction speed can be selected using INTE-

GRATOR speed variables. Finally PWM GENERATOR sets

the driver FETs duty cycles.

Schematic Diagram

20129331

FIGURE 16. Audio Input Buffer Structure

Functional Block Diagram

20129332

FIGURE 17. Signal Path Block Diagram

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