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LP3950SL 数据表(PDF) 4 Page - National Semiconductor (TI) |
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LP3950SL 数据表(HTML) 4 Page - National Semiconductor (TI) |
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4 / 31 page ![]() Absolute Maximum Ratings (Notes 1, 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. V (SW, FB, R1–2, G1–2, B1–2) (Notes 3, 4) −0.3V to +7.2V V DD1,VDD2,VDDIO,VDDA −0.3V to +6.0V Voltage on ASE, AD1, AD2 −0.3V to V DD1 +0.3V with 6.0V max Voltage on Logic Pins −0.3V to V DD_IO +0.3V with 6.0V max I (R1, G1, B1, R2, G2, B2) (Note 5) 150 mA I(V REF)10 µA Continuous Power Dissipation (Note 6) Internally Limited Junction Temperature (T J-MAX) 125˚C Storage Temperature Range −65˚C to +150˚C Maximum Lead Temperature 260˚C (Reflow soldering, 3 times) (Note 7) ESD Rating (Note 8) Human Body Model: 2 kV Machine Model: 200V Operating Ratings (Notes 1, 2) V (SW, FB, R1–2, G1–2, B1–2) 0V to 6.0V V DD1,VDD2,VDDA (Note 4) 2.7V to 2.9V V DDIO 1.65V to V DD1,2 V Voltage on ASE, AD1, AD2 0.1V to V DD1 - 0.1V Recommended Load Current 0 mA to 300 mA Junction Temperature (T J) Range −40˚C to +125˚C Ambient Temperature (T A) Range (Note 9) −40˚C to +85˚C Thermal Properties Junction-to-Ambient Thermal Resistance 72˚C/W ( θ JA), SLD32A Package (Note 10) Electrical Characteristics (Notes 2, 11) Limits in standard typeface are for T J = +25˚C. Limits in boldface type apply over the operating ambient temperature range (−40˚C ≤ T A ≤ +85˚C). Unless otherwise noted, specifications apply to Figure 1 with: V DD1 =VDD2 =VDDA = 2.8V, CVDD1 = C VDD2 =CVDDA =CVDDIO = 100 nF, COUT =CIN = 10 µF, CVREF = 100 nF, L1 = 4.7 µH and fBOOST = 2.0 MHz (Note 12). Symbol Parameter Condition Min Typ Max Units I VDD Standby Supply Current (V DD1 +VDD2 +VDDA current) NSTBY = L (register) SCK, SS, SI, NRST = H 1 5 µA No-Load Supply Current (V DD1 +VDD2 +VDDA current, boost off) NSTBY = H (reg.) EN_BOOST = L (reg.) SCK, SS, SI, NRST = H 300 400 µA Full Load Supply Current (V DD1 +VDD2 +VDDA current, boost on) (Note 13) NSTBY = H (reg.) EN_BOOST = H (reg.) SCK, SS, SI, NRST = H All Outputs Active 850 µA I VDDIO V DDIO Supply Current 1.0 MHz SCK Frequency C L =50pFatSOPin 20 µA I VDDA Audio Circuitry Supply Current (Note 14) INPUT_SEL = [10] (register) 550 µA V REF Reference Voltage(Note 15) I REF ≤ 1.0 nA Only for Test Purpose 1.230 V Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: All voltages are with respect to the potential at the GND pins (GND1–3, GND_BOOST, GND_RGB, GNDA). Note 3: Battery/Charger voltage should be above 6.0V no more than 10% of the operational lifetime. Note 4: Voltage tolerance of LP3950 above 6.0V relies on fact that VDD1,VDD2 and VDDA (2.8V) are available (ON) at all conditions. If VDD1,VDD2 and VDDA are not available (ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device. Also, VDD1,VDD2 and VDDA must be at the same electric potential. Note 5: The total load current of the boost converter should be limited to 300 mA. Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 160˚C (typ.) and disengages at TJ = 140˚C (typ.). Note 7: For detailed package and soldering specifications and information, please refer to National Semiconductor Application Note 1125: Laminate CSP/FBGA. Note 8: The Human body model is a 100 pF capacitor discharged through a 1.5 k Ω resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin. MIL-STD-883 3015.7 www.national.com 4 |
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