LP3950SL datasheet(12/31 Pages) NSC

12 / 31 page

2C Compatible Interface (Continued)

2C Timing Parameters

DD1 =VDD2 =VDDA = 2.70V to 2.90V, VDDIO = 1.65V to VDD1,2 V)

Symbol

Parameter

Limit

Units

Min

Max

Hold Time (repeated) START Condition

0.6

µs

Clock Low Time (1.65V

≤ V

DDIO < 1.80V)

3.2

µs

Clock Low Time (1.80V

≤ V

DDIO

≤ V

DD1,2V)

1.3

µs

Clock High Time (1.65V

≤ V

DDIO < 1.80V)

1200

Clock High Time (1.80V

≤ V

DDIO

≤ V

DD1,2V)

600

Setup Time for a Repeated START Condition

600

Data Hold Time (data output, delay generated by LP3950)

300

900

Data Hold Time (data input)

900

Data Setup Time

100

Rise Time of SDA and SCL

20+0.1C

300

Fall Time of SDA and SCL

15+0.1C

300

Set-up Time for STOP condition

600

Bus Free Time between a STOP and a START Condition

1.3

µs

Capacitive Load Parameter for Each Bus Line.

Load of One Picofarad Corresponds to One Nanosecond.

200

NOTE: Data guaranteed by design

20129314

FIGURE 9. I

2C Read Cycle

20129341

FIGURE 10. I

2C Timing Diagram

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