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LP3950SL 数据表(PDF) 9 Page - National Semiconductor (TI) |
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LP3950SL 数据表(HTML) 9 Page - National Semiconductor (TI) |
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9 / 31 page ![]() SPI Interface (Continued) and it has to be taken high between successive cycles. Data is clocked in on the rising edge of the SCK clock signal, while data is clocked out on the falling edge of SCK. 20129307 FIGURE 2. SPI Write Cycle 20129308 FIGURE 3. SPI Read Cycle 20129309 FIGURE 4. SPI Timing Diagram www.national.com 9 |
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