LP3950SL datasheet(10/31 Pages) NSC

10 / 31 page

SPI Timing Parameters

DD1 =VDD2 =VDDA = 2.70V to 2.90V, VDDIO = 1.80V to VDD1,2 V

Symbol

Parameter

Limit

Units

Min

Max

Cycle Time

Enable Lead Time

Enable Lag Time

Clock Low Time

Clock High Time

Data Setup Time

Data Hold Time

Data Access Time

Output Disable Time

Output Data Valid

Output Data Hold Time

SS Inactive Time

Note: Data guaranteed by design.

2C Compatible Interface

2C SIGNALS

In I

2C compatible mode, the LP3950 pin SCL is used for the

2C clock and the SDA pin is used for the I2C data. Both

these signals need a pull-up resistor according to I

2C speci-

fication. The values of the pull-up resistors are determined

by the capacitance of the bus (typ.

A1.8k). Signal timing

specifications are shown in Table I

2C Timing Parameters .

Unused pin SO can be left unconnected and pin SI must be

connected to V

DDIO or GND (address selector). Maximum bit

rate is 400 kbit/s (V

DDIO 1.80V to VDD1,2V). I

2C compatible

interface can be used down to 1.65 V

DDIO with maximum bit

rate of 200 kbit/s.

2C DATA VALIDITY

The data on the SDA line must be stable during the HIGH

period of the clock signal (SCL). In other words, state of the

data line can only be changed when CLK is LOW.

2C START AND STOP CONDITIONS

START and STOP bits classify the beginning and the end of

the I

2C session. START condition is defined as SDA signal

transition from HIGH to LOW while SCL line is HIGH. STOP

condition is defined as the SDA transition from LOW to HIGH

while SCL is HIGH. The I

2C master always generates

START and STOP bits. The I

2C bus is considered to be busy

after START condition and free after STOP condition. During

data transmission, the I

2C master can generate repeated

START conditions. First START and repeated START condi-

tions are equivalent, function-wise.

20129310

FIGURE 5. I

2C Signals: Data Validity

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