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ADC3908CSSS 数据表(PDF) 27 Page - Texas Instruments |
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ADC3908CSSS 数据表(HTML) 27 Page - Texas Instruments |
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27 / 47 page ![]() 7.3.2 Sampling Clock Input The ADC3908Dx and ADC3908Sx has a single-ended sampling clock input. To maximize the ADC SNR performance, the external sampling clock should have low jitter with a high slew rate. The ADC3908Dx and ADC3908Sx can be AC or DC coupled externally. When AC coupling, sampling clock needs to have a resistor divider such that the center voltage is around 0.9V and when DC coupling the sampling clock, center voltage needs to be around 0.9V as shown in Figure 7-6. CLK CLK 0.9V 0V 1.8V ADC ADC AVDD GND Figure 7-6. Sampling clock configuration: AC coupled (left) and DC coupled (right) www.ti.com ADC3908D025, ADC3908D065, ADC3908D125 ADC3908S025, ADC3908S065, ADC3908S125 SBASAU9 – OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: ADC3908D025 ADC3908D065 ADC3908D125 ADC3908S025 ADC3908S065 ADC3908S125 |
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