7.3.3 Digital Interface

The ADC3908Dx and ADC3908Sx family supports parallel CMOS output modes - DDR (double data rate) and

SDR (single data rate) output formats for dual and single channel devices, respectively. The output data can be

configured to 2's complement (default) or offset binary via pin control (Interface configuration table). The device

generates an output data clock and inverse data clock. For receivers that cannot use falling edge of data clock,

inverse data clock can be used to clock data.

7.3.3.1 Test Pattern

The ADC3908Dx and ADC3908Sx has a static test pattern that can be enabled via pin control (see Interface

Configuration Table). The test pattern splits each channel data into two groups, upper (D7:D4) and lower (D3:D0)

bits. Each group has a value of all zeros or a value of all 1s. Figure 7-7 shows how test pattern is implemented

for dual channel. Figure 7-8 shows how test pattern is implemented for single channel.

0

0

1

1

0

0

1

1

DCLK

Sample N

D07

Sample N-1

D03

D00

D04

0

0

1

1

0

0

1

1

DCLK

CHA

CHB

CHA

CHB

Figure 7-7. Dual Channel, Test Pattern

1

0

1

0

DCLK

Sample N

D00

Sample N-1

DCLK

D04

D03

D07

0

0

1

1

CHA

CHA

Figure 7-8. Single Channel, Test Pattern

ADC3908D025, ADC3908D065, ADC3908D125

ADC3908S025, ADC3908S065, ADC3908S125

SBASAU9 – OCTOBER 2024

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