ADC3908CSSS datasheet(23/47 Pages) TI

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7 Detailed Description

7.1 Overview

The ADC3908Dx and ADC3908Sx is a low noise, ultra-low power 8-bit high-speed single and dual channel

ADC family supporting sampling rates up to 125MSPS. With the inherent low latency architecture, the digital

output result is available after only one clock cycle. The ADC has buffered analog inputs which eases design

by isolating the input from the ADC sampling operation. The ADC3908Dx and ADC3908Sx is equipped with an

on-chip internal reference buffer and supports either single ended or differential input signaling.

The CMOS output data interface is configured as parallel DDR for dual channel devices and SDR for single

channel devices with the option of 1.8V or 3.3V logic. The device supports 2's Complement or Offset Binary

format options. The ADC3908Dx and ADC3908Sx offers DCLK as an alternate data clock for receivers that can

not capture on the DCLK falling edge when using DDR interface. Table 7-1 shows the pin mapping to supply.

Table 7-1. Device Pin to Supply Mapping

Power Supply

Device Pins

AVDD

CLK, INxP|M, RESET, M0, M1, M2, PDN

IOVDD

D0-D7, DCLK, DCLK

7.2 Functional Block Diagram

REF

ADC

Parallel

Interface

Control

Interface

RESET

AVDD

IOVDD

CLK

GND

INAP

INAM

INBP

INBM

VCM

DCLK

#8 DOUT

PDN

Figure 7-1. Dual Channel Device

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ADC3908D025, ADC3908D065, ADC3908D125

ADC3908S025, ADC3908S065, ADC3908S125

SBASAU9 – OCTOBER 2024

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