6.6 Electrical Characteristics - DC Specifications (continued)

Maximum and minimum values are specified over the operating free-air temperature range and nominal supply voltages.

Typical values are specified at TA = 25°C, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, Internal 1.2 V reference, and

–1-dBFS differential input, unless otherwise noted

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DNL

Differential nonlinearity

-0.35

±0.15

+0.35

LSB

INL

Integral nonlinearity

-0.6

±0.25

+0.6

LSB

VOS_ERR

Offset error

-2.75

±1

-2.75

LSB

VOS_DRIFT

Offset drift over temperature

0.001

LSB/ºC

GAINERR

Gain error

Internal Reference

±0.8

%FSR

GAINDRIFT

Gain drift over temperature

Internal Reference

-102

ppm/ºC

DC ACCURACY (125 MSPS)

No missing codes

8

bits

DNL

Differential nonlinearity

-0.35

±0.15

+0.35

LSB

INL

Integral nonlinearity

-0.6

±0.25

+0.6

LSB

VOS_ERR

Offset error

-2.75

±1

2.75

LSB

VOS_DRIFT

Offset drift over temperature

0.001

LSB/ºC

GAINERR

Gain error

Internal Reference

±0.8

%FSR

GAINDRIFT

Gain drift over temperature

Internal Reference

-102

ppm/ºC

ADC ANALOG INPUT (INAP/M, INBP/M)

FS

Input full scale

Differential

1.9

Vpp

Single-ended

0.95

Vpp

CIN

Differential input Capacitance

FIN = 100 kHz

7

pF

VCM

Input common mode voltage

VOCM -

50mV

1.275

VOCM +

50mV

V

VOCM

Output common mode voltage

1.25

V

BW

Analog Input Bandwidth (-3dB)

150

MHz

CLOCK INPUT

Input clock frequency

ADC3908D125, ADC3908S125

5

125

MHz

ADC3908D065, ADC3908S065

5

65

MHz

ADC3908D025, ADC3908S025

5

25

MHz

VIH

High level input voltage

AVDD -

0.3

1.8

Vpp

VIL

Low level input voltage

0

AVSS +

0.3

V

CIN

Input capacitance

0.5

pF

Clock duty cycle

45

50

55

%

DIGITAL INPUTS (RESET, PDN, M0, M1, M2)

VIH

High level input voltage

1.4

V

VIL

Low level input voltage

0.4

V

IIH

High level input current

90

150

uA

IIL

Low level input current

-150

-90

uA

CI

Input capacitance

1.5

pF

DIGITAL CMOS OUTPUTS (D0:D07)

Output data rate

per CMOS output pin

250

Mbps

VOH

High level output voltage

ILOAD = -400 uA

IOVDD -

0.1

IOVDD

V

VOL

Low level output voltage

ILOAD = 400 uA

0.1

V

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