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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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M69KB128AA 数据表(PDF) 52 Page - STMicroelectronics |
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M69KB128AA 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 68 page  9 DC and AC parameters M69KB128AA 52/68 Table 20. Clock Related AC Timings Table 21. Synchronous Burst Read AC Characteristics Symbol Alt. Parameter M69KB128AA Unit 104MHz 80MHz 66MHz Min Max Min Max Min Max fCLk fCLk Clock frequency 104 80 66 MHz tKHKH tCLK Clock Period 9.62 12.5 15 ns tR tF tKHKL Clock Rise Time Clock Fall Time 1.6 1.8 2.0 ns tKHKL tKLKH tKP Clock High to Clock Low Clock Low to Clock High 34 5 ns tKHDZ tKHZ Clock High to Output Hi-Z 3 8 3 8 3 8 ns tKHDX tKLZ Clock High to Output Transition 2 5 2 5 2 5 ns Symbol Alt. Parameter(1) M69KB128AA Unit 104MHz 80MHz 66MHz Min Max Min Max Min Max tAVQV tAA Address Valid to Output Valid (Fixed Latency) 70 70 85 ns tLLQV tAADV Latch Enable Low to Output Valid (Fixed Latency) 70 70 85 ns tKHQV1 tABA Burst to Read Access Time (Variable Latency) 35 46 55 ns tKHQV2 tACLK Clock High to Output Delay 7 9 11 ns tGLQV tBOE Delay From Output Enable Low to Output Valid in Burst mode 20 20 20 ns tEHEL (2) tCBPH Chip Enable High between Subsequent Operations in Full-Synchronous or NOR- Flash mode. 56 8 ns tELEH (2) tCEM Chip Enable Pulse Width 4 4 4 µs tELTV tLLTV tCEW Chip Enable Low to WAIT Valid Latch Enable Low to WAIT Valid 1 7.5 1 7.5 1 7.5 ns tELQV tCO Chip Enable Low to Output Valid 70 70 85 ns tELKH tCSP Chip Enable Low to Clock High 3 4 5 ns |
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