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M69KB128AA 数据表(PDF) 17 Page - STMicroelectronics

部件名 M69KB128AA
功能描述  128 Mbit (8Mb x16) 1.8V Supply, Burst PSRAM
PDF  68 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

M69KB128AA 数据表(HTML) 17 Page - STMicroelectronics

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M69KB128AA
5 Standard asynchronous operating modes
17/68
Table 3.
Standard Asynchronous Operating Modes
Asynchronous
Modes(1)
1.
The Clock signal, K, must remain Low in asynchronous operating mode.
Power
L
E
W
G
UB
LB
WAIT
CR
A19 A18
A0-A17
A20-A22
DQ0-
DQ7
DQ8-
DQ15
Word Read
Active
(ICC)
VIL
VIL
VIH
VIL VIL VIL
Low-
Z
VIL
Valid
Output
Valid
Output
Valid
Lower Byte
Read
VIL VIH VIL
VIL
Valid
Output
Valid
High-Z
Upper Byte
Read
VIL VIL VIH
VIL
Valid
High-Z
Output
Valid
Word Write
VIL
X
VIL VIL
VIL
Valid
Input
Valid
Input
Valid
Lower Byte
Write
X
VIH VIL
VIL
Valid
Input
Valid
Invalid
Upper Byte
Write
X
VIL VIH
VIL
Valid
Invalid
Input
Valid
Read
Configuration
Register
(CR Controlled
Method)
VIH VIL VIL VIL
VIH
00(RCR)
10(BCR)
X1(DIDR)
(2)
2.
A18 and A19 are used to select the BCR, RCR or DIDR registers.
X
BCR/
RCR/DIDR
Content
Program
Configuration
Register (CR
Controlled)(3)
3.
BCR and RCR only.
VIH
XX
X
00(RCR)
10(BCR)
(2)
BCR/
RCR
Data
High-Z
No Operation
Active
(ICC)
X
XX
X
X
VIL
XX
X
X
Deep
Power-Down(4)
4.
Bit 4 of the Refresh Configuration Register must be set to ‘0’, bit 4 (BCR4) of the Bus Configuration Register must be set to
‘0’, and E has to be maintained High, VIH, during Deep Power-Down mode.
Deep
Power-
Down
(ICCPD)
VIH
XX
X
X
High-
Z
X
X
X
X
High-Z
Standby
Standby
(IPASR)
VIH
XX
X
X
VIL
X
X
X
High-Z



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