M69KB128AA datasheet(20/68 Pages) STMICROELECTRONICS

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6 Synchronous operating modes

M69KB128AA

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6.3.1

Variable Latency

In Variable Latency mode, the latency programmed in the BCR is not guaranteed and is

maintained only if there is no conflict with a refresh operation.

The Latency set in the BCR is applicable only for an initial burst read access, when no refresh

request is pending. For a given latency value, the Variable Latency mode allows higher

operating frequencies than the Fixed Latency mode (see Table 4: Operating Frequency versus

Latency and Figure 3: Latency Configuration (Variable Latency mode, no Refresh collision)).

Burst Write operations are always performed at fixed latency, even if BCR14 is configured to

Variable Latency (see Section 6.3.2: Fixed Latency).

Monitoring of the WAIT signal is recommended for reliable operation in this mode.

See Figure 24. and Figure 31 for details on Synchronous Burst Read and Write AC waveforms

in Variable Latency mode.

6.3.2

Fixed Latency

The latency programmed in the BCR is the real latency. The number of clock cycles is

calculated by taking into account the time necessary for a refresh operation and the time

necessary for an initial Burst access. This limits the operating frequency for a given latency

value (see Table 4: Operating Frequency versus Latency and Figure 4: Latency Configuration

(Fixed Latency mode)).

It is recommended to use the Fixed Latency mode if the microcontroller cannot monitor the

WAIT signal.

6.3.3

Row Boundary crossing

The M69KB128AA features 128-Word rows. Row boundary crossings between adjacent rows

may occur during Burst Read and Write operations. Row boundary crossings are not handled

automatically by the PSRAM.

The microcontroller must stop the Burst operation at the row boundary and restart it at the

beginning of the next row. Burst operations must be stopped by driving the Chip Enable signal,

E, High, after the WAIT signal falling edge. E must transition:

●

Before the third Clock cycle after the WAIT signal goes Low if BCR[8] = 0

●

Before the fourth Clock cycle after WAIT signal goes Low if BCR[8] = 1.

Refer to Figure 26 and Figure 30 for details on how to manage row boundary crossings during

burst operations.

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